中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

60 records (took 0.053 seconds)

    METHOD OF ENHANCED OXIDATION OF MOS TRANSISTOR GATE CORNERS
    22.
    发明申请
    METHOD OF ENHANCED OXIDATION OF MOS TRANSISTOR GATE CORNERS 审中-公开
    MOS晶体管栅极的增强氧化方法

    公开(公告)号：WO02089180A3

    公开(公告)日：2003-02-06

    申请号：PCT/US0149571

    申请日：2001-12-27

    Applicant: IBM

    Inventor： DOKUMACI OMER ,  GLUSCHENKOV OLEG ,  HEDGE SURYANARAYAN G ,  KAPLAN RICHARD ,  KHARE MUKESH

    IPC: H01L29/786 ,  H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L21/3205 ,  H01L21/31

    CPC classification number: H01L21/28176 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/28247 ,  H01L29/42368 ,  H01L29/4941

    Abstract: A method of enhancing the rate of transistor gate corner oxidation, without significantly increasing the thermal budget of the overall processing scheme is provided. Specifically, the method of the present invention includes implanting ions into gate corners (20) of a Si-containing transistor having a gate conductor (16) and a dielectric cap (18), and exposing the transistor including implanted transistor gate corners (20) to an oxidizing ambient. The ions employed in the implant step include Si, non-retarding oxidation ions such as O, Ge, As, B, P, In, Sb, Ga, F, C1, He, Ar, Kr, and Xe; and mixtures thereof.

    Abstract translation: 提供了一种提高晶体管栅极角氧化速率的方法，而不显着增加整体处理方案的热预算。 具体地，本发明的方法包括将离子注入到具有栅极导体（16）和电介质盖（18）的含硅晶体管的栅极拐角（20）中，并且使包括注入的晶体管栅极角（20）的晶体管暴露， 到氧化环境。 在注入步骤中使用的离子包括Si，不延迟氧化离子如O，Ge，As，B，P，In，Sb，Ga，F，Cl，He，Ar，Kr和Xe; 及其混合物。

    SILICON GERMANIUM HETEROJUNCTION BIPOLAR TRANSISTOR STRUCTURE AND METHOD
    23.
    发明申请
    SILICON GERMANIUM HETEROJUNCTION BIPOLAR TRANSISTOR STRUCTURE AND METHOD 审中-公开
    硅锗绝缘双极晶体管结构与方法

    公开(公告)号：WO2008134686A3

    公开(公告)日：2009-12-30

    申请号：PCT/US2008061938

    申请日：2008-04-30

    Applicant: IBM ,  KRISHNASAMY RAJENDRAN ,  GLUSCHENKOV OLEG ,  SCHONENBERG KATHRYN T

    Inventor： KRISHNASAMY RAJENDRAN ,  GLUSCHENKOV OLEG ,  SCHONENBERG KATHRYN T

    IPC: H01L21/331

    CPC classification number: H01L29/66242 ,  H01L21/2253 ,  H01L21/26513 ,  H01L21/324 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/1004 ,  H01L29/7378

    Abstract: Disclosed is an improved semiconductor structure 150 (e.g., a silicon germanium (SiGe) hetero-junction bipolar transistor 100) having a narrow essentially interstitial-free SIC pedestal 120 with minimal overlap of the extrinsic base 104. Also, disclosed is a method of forming the transistor which uses laser annealing, as opposed to rapid thermal annealing, of the SIC pedestal to produce both a narrow SIC pedestal and an essentially interstitial-free collector. Thus, the resulting SiGe HBT transistor can be produced with narrower base 103 and collector space-charge regions than can be achieved with conventional technology.

    Abstract translation: 公开了一种改进的半导体结构150（例如，硅锗（SiGe）异质结双极晶体管100），其具有窄的基本上无间隙的SIC基座120，其外部基极104具有最小的重叠。此外，公开了一种形成 使用与SIC基座的快速热退火相反的激光退火以产生窄SIC基座和基本上无间隙的收集器的晶体管。 因此，所得到的SiGe HBT晶体管可以制造成具有比用常规技术可以实现的更窄的基极103和集电极空间电荷区域。

    EPITAXY OF SILICON-CARBON SUBSTITUTIONAL SOLID SOLUTIONS BY ULTRA-FAST ANNEALING OF AMORPHOUS MATERIAL
    24.
    发明申请
    EPITAXY OF SILICON-CARBON SUBSTITUTIONAL SOLID SOLUTIONS BY ULTRA-FAST ANNEALING OF AMORPHOUS MATERIAL 审中-公开
    通过超弹性非晶态材料退火的硅碳取代固体溶液外延

    公开(公告)号：WO2007112432A3

    公开(公告)日：2009-03-26

    申请号：PCT/US2007065324

    申请日：2007-03-28

    Applicant: IBM ,  LIU YAOCHENG ,  GLUSCHENKOV OLEG ,  RIM KERN ,  MADAN ANITA ,  HOLT JUDSON

    Inventor： LIU YAOCHENG ,  GLUSCHENKOV OLEG ,  RIM KERN ,  MADAN ANITA ,  HOLT JUDSON

    IPC: H01L21/20 ,  H01L21/36

    CPC classification number: H01L21/2022 ,  H01L21/2026 ,  H01L21/268 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/6656 ,  H01L29/78 ,  H01L29/7848

    Abstract: Expitaxial substitutional solid solutions of silicon carbon (101 ) can be obtained by an ultra-fast anneal of an amorphous carbon-containing silicon material. The anneal is performed at a temperature above the recrystallization point, but below the melting point of the material and preferably lasts for less than 100 milliseconds in this temperature regime. The anneal is preferably a flash anneal or laser anneal. This approach is able to produce epitaxial silicon and carbon-containing materials (101 ) with a substantial portion of the carbon atoms at substitutional lattice positions. The approach is especially useful in CMOS processes and other electronic device manufacture where the presence of epitaxial Si1-yCy, y

    Abstract translation: 可以通过非晶态含碳硅材料的超快速退火获得硅碳（101）的外延替代固溶体。 退火在高于再结晶点的温度下进行，但低于材料的熔点，并且在该温度范围内优选持续小于100毫秒。 退火优选是闪光退火或激光退火。 该方法能够产生具有替代晶格位置的大部分碳原子的外延硅和含碳材料（101）。 该方法在CMOS工艺和其他电子器件制造中特别有用，其中外延Si1-yCy，y <0.1对于应变工程或带隙工程是需要的。

    DUAL STRESSED SOI SUBSTRATES
    25.
    发明申请
    DUAL STRESSED SOI SUBSTRATES 审中-公开
    双应力SOI衬底

    公开(公告)号：WO2006065759A3

    公开(公告)日：2007-06-14

    申请号：PCT/US2005044957

    申请日：2005-12-13

    Applicant: IBM ,  CHIDAMBARRAO DURESETI ,  DOKUMACI OMER H ,  DORIS BRUCE B ,  GLUSCHENKOV OLEG ,  ZHU HUILONG

    Inventor： CHIDAMBARRAO DURESETI ,  DOKUMACI OMER H ,  DORIS BRUCE B ,  GLUSCHENKOV OLEG ,  ZHU HUILONG

    IPC: H01L21/84 ,  H01L27/01

    CPC classification number: H01L21/84 ,  H01L27/1203 ,  H01L29/7843 ,  Y10S438/938

    Abstract: The present invention provides a strained-Si structure, in which the nFET regions of the structure are strained in tension and the pFET regions of the structure are strained in compression. Broadly the strained-Si structure comprises a substrate; a first layered stack atop the substrate, the first layered stack comprising a compressive dielectric layer atop the substrate and a first semiconducting layer atop the compressive dielectric layer, wherein the compressive dielectric layer transfers tensile stresses to the first semiconducting layer, and a second layered stack atop the substrate, the second layered stack comprising an tensile dielectric layer atop the substrate and a second semiconducting layer atop the tensile dielectric layer, wherein the tensile dielectric layer transfers compressive stresses to the second semiconducting layer. The tensile dielectric layer and the compressive dielectric layer preferably comprise nitride, such as Si 3 N 4 .

    Abstract translation: 本发明提供一种应变Si结构，其中该结构的nFET区域被拉紧并且该结构的pFET区域被压缩而变形。 广义上，应变Si结构包括基底; 所述第一层叠堆叠包括位于所述衬底顶部的压缩介电层和位于所述压缩介电层顶部的第一半导体层，其中所述压缩介电层将拉伸应力传递到所述第一半导体层，以及第二层叠堆叠 所述第二层叠堆叠包括位于所述衬底顶部的拉伸电介质层和位于所述拉伸介电层顶部的第二半导体层，其中所述拉伸介电层将压缩应力传递到所述第二半导体层。 拉伸介电层和压电介电层优选包括氮化物，例如Si 3 N 4 N 4。

    DUAL GATE OXIDE PROCESS FOR UNIFORM OXIDE THICKNESS
    28.
    发明申请
    DUAL GATE OXIDE PROCESS FOR UNIFORM OXIDE THICKNESS 审中-公开
    用于均匀氧化物厚度的双栅氧化工艺

    公开(公告)号：WO0237561A2

    公开(公告)日：2002-05-10

    申请号：PCT/US0143859

    申请日：2001-11-06

    Applicant: IBM ,  INFINEON TECHNOLOGIES AG

    Inventor： TEWS HELMUT ,  WEYBRIGHT MARY ,  KUDELKA STEPHAN ,  GLUSCHENKOV OLEG ,  HEGDE SURI

    IPC: H01L21/265 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/8242 ,  H01L29/51

    CPC classification number: H01L21/28185 ,  H01L21/26506 ,  H01L21/28202 ,  H01L21/2822 ,  H01L21/28238 ,  H01L21/823462 ,  H01L27/10873 ,  H01L29/518 ,  Y10S438/981

    Abstract: A process for forming dual gate oxides of improved oxide thickness uniformity for use in high performance DRAM systems or logic circuits, comprising:a) growing a sacrificial oxide layer on a substrate;b) implanting a dopant through the sacrificial oxide layer;c) implanting a first dosage of nitrogen ions in the absence of a photoresist to form a nitrided silicon layer; d) subjecting the substrate to a rapid thermal anneal for a sufficient time and at a sufficient temperature to allow nitrogen to diffuse to the silicon/oxide interface;e) masking the substrate with a photoresist to define the locations of the thin oxides of the dual gate oxide;f) implanting a second dosage of nitrogen ions through the photoresist;g) stripping the photoresist and the sacrificial oxide layers; and h) growing by oxidation gate oxide layers characterized by improved oxide thickness uniformity in the nitrogen ion implanted areas in the thin and thick oxides.

    Abstract translation: 一种用于形成用于高性能DRAM系统或逻辑电路的改进的氧化物厚度均匀性的双栅极氧化物的方法，包括：a）在衬底上生长牺牲氧化物层; b）通过所述牺牲氧化物层注入掺杂剂; c） 不存在光致抗蚀剂的氮离子的第一剂量形成氮化硅层; d）对衬底进行快速热退火足够的时间和足够的温度以使氮气扩散到硅/氧化物界面; e）用光致抗蚀剂掩蔽衬底以限定双重氧化物的薄氧化物的位置 栅极氧化物; f）通过光致抗蚀剂注入第二剂量的氮离子; g）剥离光致抗蚀剂和牺牲氧化物层; 和h）通过氧化栅氧化层生长，其特征在于在薄和厚的氧化物中的氮离子注入区域中改善的氧化物厚度均匀性。

    Sloped epitaxy buried contact
    29.
    发明专利
    Sloped epitaxy buried contact 未知

    公开(公告)号：AU2021291163B2

    公开(公告)日：2024-05-02

    申请号：AU2021291163

    申请日：2021-06-04

    Applicant: IBM

    Inventor： LI TAO ,  KANG TSUNG-SHENG ,  XIE RUILONG ,  REZNICEK ALEXANDER ,  GLUSCHENKOV OLEG

    IPC: H01L27/088

    Abstract: Semiconductor device designs having a buried power rail (602) with a sloped epitaxy buried contact (1702) are provided. In one aspect, a semiconductor FET device includes: at least one gate disposed on a substrate (202); source and drains (906) on opposite sides of the at least one gate, wherein at least one of the source and drains (906) has a sloped surface (1402); a buried power rail (602) embedded in the substrate (202); and a buried contact (1702) that connects the buried power rail (602) to the sloped surface (1402) of the at least one source and drain (906). Sidewall spacers (502) separate the buried power rail (602) from the substrate (202). A top of the sloped surface (1402) of the at least one source and drain (906) is above a top surface of the buried contact (1702).Methods of forming a semiconductor FET device are also provided.

    30.
    发明专利
    未知

    公开(公告)号：AT487234T

    公开(公告)日：2010-11-15

    申请号：AT05853786

    申请日：2005-12-13

    Applicant: IBM

    Inventor： CHIDAMBARRAO DURESETI ,  DOKUMACI OMER H ,  DORIS BRUCE ,  GLUSCHENKOV OLEG ,  ZHU HUILONG

    IPC: H01L21/84 ,  H01L27/01

    Abstract: The present invention provides a strained-Si structure, in which the nFET regions of the structure are strained in tension and the pFET regions of the structure are strained in compression. Broadly the strained-Si structure comprises a substrate; a first layered stack atop the substrate, the first layered stack comprising a compressive dielectric layer atop the substrate and a first semiconducting layer atop the compressive dielectric layer, wherein the compressive dielectric layer transfers tensile stresses to the first semiconducting layer; and a second layered stack atop the substrate, the second layered stack comprising an tensile dielectric layer atop the substrate and a second semiconducting layer atop the tensile dielectric layer, wherein the tensile dielectric layer transfers compressive stresses to the second semiconducting layer. The tensile dielectric layer and the compressive dielectric layer preferably comprise nitride, such as Si 3 N 4 .

Patent Agency Ranking