公开(公告)号：ID29224A

公开(公告)日：2001-08-16

申请号：ID20010796

申请日：1999-09-03

Applicant: QUALCOMM INC

Inventor： SIH GILBERT C ,  ZOU QIUZHEN ,  KANG INYUP ,  FEVRIER IAN J

IPC: G01S1/00 ,  G01S19/23 ,  G01S19/24 ,  G01S19/25 ,  G01S19/29 ,  G01S19/36 ,  G01S19/48 ,  G01S5/14

Abstract: The present invention is a novel and improved method and apparatus for performing position location in wireless communications system. One embodiment comprises a method for performing position location using a set of signals transmitted from a set of satellites including the steps of storing coarse search data, performing a coarse search on said coarse search data for each satellite from said set of satellites, receiving fine search data, performing a set of fine searches on said fine search data, each fine search being performed on a different time segment of said fine search data, and reporting results.

公开(公告)号：AU2986099A

公开(公告)日：1999-10-11

申请号：AU2986099

申请日：1999-03-04

Applicant: QUALCOMM INC

Inventor： SIH GILBERT C ,  ZOU QUIZHEN ,  JHA SANJAY K ,  KANG INYUP ,  LIN JIAN ,  MOTIWALA QUAEED ,  JOHN DEEPU ,  ZHANG LI ,  ZHANG HAITAO ,  LEE WAY-SHING ,  SAKAMAKI CHARLES E ,  KANTAK PRASHANT A

IPC: G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F12/08 ,  G06F12/0886 ,  G06F15/78

Abstract: A circuit for digital signal processing calls for the use of a variable length instruction set. An exemplary DSP includes a set of three data buses (108, 110, 112) over which data may be exchanged with a register bank (120) and three data memories (102, 103, 104). A register bank (120) may be used that has registers accessible by at least two processing units (128, 130). An instruction fetch unit (156) may be included that receives instructions of variable length stored in an instruction memory (152). The instruction memory (152) may be separate from the set of three data memories (102, 103, 104).

公开(公告)号：CA2324219A1

公开(公告)日：1999-09-23

申请号：CA2324219

申请日：1999-03-04

Applicant: QUALCOMM INC

Inventor： SAKAMAKI CHARLES E ,  KANTAK PRASHANT A ,  SIH GILBERT C ,  LEE WAY-SHING ,  ZHANG HAITAO ,  ZHANG LI ,  JOHN DEEPU ,  ZOU QUIZHEN ,  JHA SANJAY K ,  KANG INYUP ,  LIN JIAN ,  MOTIWALA QUAEED

IPC: G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F12/08 ,  G06F12/0886 ,  G06F15/78

Abstract: A circuit for digital signal processing calls for the use of a variable length instruction set. An exemplary DSP includes a set of three data buses (108, 110, 112) over which data may be exchanged with a register bank (120) and three data memories (102, 103, 104). A register bank (120) may be used that has registers accessible by at least two processing units (128, 130). An instruction fetch unit (156) may be included that receives instructions of variable length stored in an instruction memory (152). The instruction memory (152) may be separate from the set of three data memories (102, 103, 104).

公开(公告)号：ES2465220T3

公开(公告)日：2014-06-05

申请号：ES11009956

申请日：2007-11-14

Applicant: QUALCOMM INC

Inventor： SHIM BYONGHYO ,  KANG INYUP ,  ABRISHAMKAR FARROKH ,  SAMBHWANI SHARAD DEEPAK

IPC: H04B1/707 ,  H04L25/03

Abstract: Un procedimiento en un sistema de comunicaciones de acceso múltiple inalámbrico que comprende: realizar detección (814) de datos en una señal recibida para obtener una señal detectada para un primer conjunto de canales de codificación para un sector de célula; reconstruir una señal (816) para el primer conjunto de canales de codificación basándose en la señal detectada; cancelar (818) la señal reconstruida para el primer conjunto de canales de codificación a partir de la señal recibida; y realizar detección (814) de datos, reconstrucción (816) y cancelación (818) para al menos un conjunto adicional de canales de código para otro sector de célula.

公开(公告)号：ES2358623T3

公开(公告)日：2011-05-12

申请号：ES08013899

申请日：1999-09-03

Applicant: QUALCOMM INC

Inventor： KANG INYUP ,  ZOU QUIZHEN ,  SIH GILBERT C

IPC: G01S5/00 ,  G01S1/00 ,  G01S1/04 ,  G01S19/23 ,  G01S19/25 ,  G01S19/30 ,  G01S19/48 ,  H04M1/725 ,  H04Q7/34

Abstract: Dispositivo movil (10) que comprende un receptor configurado para recibir una primera senal de un satelite, incluyendo la primera senal un mensaje de navegacion extendido con una secuencia PN; un correlacionador para correlacionar primeras muestras de senale con varios desfase de la secuencia PN; y caracterizado por: un integrador coherente (104) configurado para integrar coherentemente los productos de correlacion resultantes para un intervalo de integracion coherente particular, en el cual, cuando el intervalo de integracion coherente abarca un limite de datos del mensaje de navegacion, la integracion coherente se divide en una seccion anterior al limite de datos del mensaje de navegacion y una seccion posterior al limite de datos del mensaje de navegacion.

公开(公告)号：CA2727202A1

公开(公告)日：2009-12-30

申请号：CA2727202

申请日：2009-01-21

Applicant: QUALCOMM INC

Inventor： PARK JONG HYEON ,  BANISTER BRIAN CLARK ,  KANG INYUP ,  KIM JE WOO ,  HURT JAMES Y ,  BREHLER MATTHIAS

IPC: H04L1/06

Abstract: Space time coding (STC) may be applied at the transmitter adding redundant information in both space and time dimensions. At the receiver, the received STC signal may be decoded using a spatial multiplexing MIMO decoding, for example, based on either Minimum Mean Square Error (MMSE) or maximum-likelihood (ML) algorithms. A selective STC decoder may incorporate both the conventional maximum ratio combining (MRC) decoding scheme and a MIMO decoding scheme. One of the STC decoding schemes may be selected, for example, based on estimated channel conditions in order to achieve a trade-off between error rate performance and computational complexity. Components used for a non-selected scheme may be powered down.

公开(公告)号：CA2436783C

公开(公告)日：2008-04-01

申请号：CA2436783

申请日：2001-11-16

Applicant: QUALCOMM INC

Inventor： KANG INYUP

IPC: H04B1/7117 ,  H04B1/712

Abstract: A deskew buffer 410 arrangement in a CDMA receiver allows for accurate combining of symbols from a plurality of demodulator fingers, 402 and 404, without any symbol losses when the data rate is changed. A single deskew buffer 410 is coupled to a plurality of demodulator fingers, each of which demodulate an assigned multipath. The symbols are written into the deskew buffer 410 according to a PN count value modified by a predetermined bit pattern. The demodulator finger is able to demodulate a plurality of data rates corresponding to a plurality of Walsh lengths. Each data rate is assigned a corresponding deskew index. The PN count value represents an address within the deskew buffer 410. The lower bits of the PN count, where the number of bits corresponds to the deskew index, are truncated and replaced with the predetermined bit pattern. In one embodiment the predetermined bit pattern is all ones.

公开(公告)号：DE69925720T2

公开(公告)日：2006-03-16

申请号：DE69925720

申请日：1999-03-04

Applicant: QUALCOMM INC

Inventor： SIH C ,  ZOU QUIZHEN ,  JHA K ,  KANG INYUP ,  LIN JIAN ,  MOTIWALA QUAEED ,  JOHN DEEPU ,  ZHANG LI ,  ZHANG HAITAO ,  LEE WAY-SHING ,  SAKAMAKI E ,  KANTAK A

IPC: G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F12/08 ,  G06F12/0886 ,  G06F15/78

Abstract: A circuit for digital signal processing calls for the use of a variable length instruction set. An exemplary DSP includes a set of three data buses (108, 110, 112) over which data may be exchanged with a register bank (120) and three data memories (102, 103, 104). A register bank (120) may be used that has registers accessible by at least two processing units (128, 130). An instruction fetch unit (156) may be included that receives instructions of variable length stored in an instruction memory (152). The instruction memory (152) may be separate from the set of three data memories (102, 103, 104).

公开(公告)号：AT297567T

公开(公告)日：2005-06-15

申请号：AT99911150

申请日：1999-03-04

Applicant: QUALCOMM INC

Inventor： SIH GILBERT C ,  ZOU QUIZHEN ,  JHA SANJAY K ,  KANG INYUP ,  LIN JIAN ,  MOTIWALA QUAEED ,  JOHN DEEPU ,  ZHANG LI ,  ZHANG HAITAO ,  LEE WAY-SHING ,  SAKAMAKI CHARLES E ,  KANTAK PRASHANT A

IPC: G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F12/08 ,  G06F12/0886 ,  G06F15/78

Abstract: A circuit for digital signal processing calls for the use of a variable length instruction set. An exemplary DSP includes a set of three data buses (108, 110, 112) over which data may be exchanged with a register bank (120) and three data memories (102, 103, 104). A register bank (120) may be used that has registers accessible by at least two processing units (128, 130). An instruction fetch unit (156) may be included that receives instructions of variable length stored in an instruction memory (152). The instruction memory (152) may be separate from the set of three data memories (102, 103, 104).

公开(公告)号：ES2230888T3

公开(公告)日：2005-05-01

申请号：ES99945487

申请日：1999-09-03

Applicant: QUALCOMM INC

Inventor： KANG INYUP ,  SIH GILBERT C ,  ZOU QIUZHEN

IPC: G01S5/00 ,  G01S19/23 ,  G01S19/25 ,  G01S19/29 ,  G01S19/30 ,  H04Q7/34 ,  G01S5/14

Abstract: Un método para realizar localización de posición que comprende: recibir muestras de señal; y generar una secuencia de adquisición basta; caracterizado por: rotar dicha secuencia de adquisición basta produciendo una secuencia de adquisición basta rotada; y aplicar dicha secuencia de adquisición basta rotada a dichas muestras de señal en un conjunto de desplazamientos de tiempo produciendo datos de salida correlacionados.