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    Method for erasing memory cell of type FAMOS and corresponding memory-cell device, by electrical means
    22.
    发明专利
    Method for erasing memory cell of type FAMOS and corresponding memory-cell device, by electrical means 未知

    公开(公告)号：FR2823363A1

    公开(公告)日：2002-10-11

    申请号：FR0104621

    申请日：2001-04-05

    Applicant: ST MICROELECTRONICS SA

    Inventor： FOURNEL RICHARD ,  DRAY CYRILLE ,  CASPAR DANIEL

    IPC: G11C16/02 ,  G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C16/14

    Abstract: The method is for electrical erasing of a memory cell (CM) of type FAMOS, which comprises a p-MOS transistor with a floating gate which is not connected. The erasing is by the application of determined voltages to the bulk (B), the source (S) and the drain (D) of the transistor by an erasing module (MEF), that is a voltage VB to the bulk, which is higher than at last 4-6 V, with still lower voltages VS and VD applied to the source and the drain, respectively, and below a limiting voltage which causes the destruction of the cell, which is about 10 V. The difference between voltages applied to the source and the drain is non-null and positive, and below a predetermined threshold, which is about 1 V. For example, in the case of 0.18 micrometer technology, the source voltage is about 1 V, the drain voltage null, and the bulk voltage about 7-8 V, and the erasing takes about 1 minute. The difference between the source and the drain voltages is variable in the course of erasing process. The memory device comprises an electrically erasable memory cell (CM) of type FAMOS. The p-MOS transistor of the memory cell has a standard linear configuration, or more advantageously a ring ocnfiguration which comprises a central electrode surrounded by the gate and a peripheral electrode. The device comprises programming means for writing data into the memory cell, reading means for reading the content of the memory cell, and control means for selectively connecting the means for programming, reading and erasing of the memory cell. The device comprises several electrically erasable memory cells of type FAMOS. The memory device is a part of an integrated circuit.

    23.
    发明专利
    未知

    公开(公告)号：FR2820545A1

    公开(公告)日：2002-08-09

    申请号：FR0101442

    申请日：2001-02-02

    Applicant: ST MICROELECTRONICS SA

    Inventor： FOURNEL RICHARD ,  SEDJAI LEILA

    IPC: G11C16/34 ,  G11C29/34 ,  H01L21/8247

    Abstract: The invention relates to a method for the simultaneous verification of a first electrical state of a group of N cells from a non-volatile memory. The inventive method is characterised in that it comprises the following steps: the N memory cells (CE) to be verified and the verification cell (Cveri) are read and selected simultaneously; the N signals which are read are added together to produce a sum signal; the sum signal is compared to the signal which is read on the verification cell (Cveri) in order to provide a certain state signal when the sum signal is less than the signal which is read on the verification cell (Cveri), indicating that the N memory cells are in said electrical state, and another electrical state signal when the sum signal is greater than the signal which is read on the verification cell, indicating that at least one memory cell is not in said electrical state.

    25.
    发明专利
    未知

    公开(公告)号：FR2801719B1

    公开(公告)日：2002-03-01

    申请号：FR9915114

    申请日：1999-11-30

    Applicant: ST MICROELECTRONICS SA

    Inventor： FOURNEL RICHARD ,  VARISCO LAURA

    IPC: G11C7/08 ,  G11C7/12 ,  G11C16/24 ,  G11C16/28

    Abstract: A device for reading a memory including precharging circuits for precharging the inputs of a differential amplifier to a precharging voltage. The precharging voltage may be at an intermediate voltage level between a precharging voltage level of the bit lines and the voltage level of the logic supply voltage. This provides for a very fast build-up, during a following evaluation phase, of the output of the amplifier in a state corresponding to that of the cell being read. An internal detection circuit may also be included to detect an end of the precharging to stop the precharging circuit and activate the read current generator for the evaluation phase.

    28.
    发明专利
    未知

    公开(公告)号：FR2875352B1

    公开(公告)日：2007-05-11

    申请号：FR0409650

    申请日：2004-09-10

    Applicant: ST MICROELECTRONICS SA

    Inventor： GENDRIER PHILIPPE ,  CANDELIER PHILIPPE ,  FOURNEL RICHARD

    IPC: H03M13/05 ,  G06F11/10 ,  H03M13/09 ,  H03M13/19 ,  H03M13/35 ,  H03M13/37

    Abstract: A method is for detecting and correcting errors for a memory storing at least one code block including information data and control data. The method includes reading and decoding each element of the at least one code block to deliver an information item representative of a number of errors in the at least one code block. The method further includes, when the number of errors exceeds one, modifying a parameter of the read by a chosen value, and performing a reading and decoding of the at least one code block again to obtain a new error information item.

    ARCHITECTURE DE MEMOIRE A LIGNES D'ECRITURE SEGMENTEES
    29.
    发明专利
    ARCHITECTURE DE MEMOIRE A LIGNES D'ECRITURE SEGMENTEES 未知

    公开(公告)号：FR2871921A1

    公开(公告)日：2005-12-23

    申请号：FR0406532

    申请日：2004-06-16

    Applicant: ST MICROELECTRONICS SA

    Inventor： DRAY CYRILLE ,  BARASINSKI SEBASTIEN ,  LASSEUGUETTE JEAN ,  FREY CHRISTOPHE ,  FOURNEL RICHARD

    IPC: G11C7/18 ,  G11C8/10 ,  G11C11/16

    Abstract: L'invention concerne un dispositif de mémoire, comprenant au moins une ligne d'écriture segmentée (10) formée d'au moins un segment d'écriture, dotée de moyens de programmation (90), lesdits moyens de programmation (90) étant commandés par des moyens d'adressage de ligne (190) en mode écriture dudit dispositif de mémoire, pour programmer au moins une cellule mémoire (30) couplée à ladite ligne d'écriture segmentée, une ligne de bit de lecture (150) étant reliée à un circuit de lecture (110) pour lire le contenu de ladite cellule en mode lecture dudit dispositif de mémoire, caractérisé en ce que ladite ligne de bit de lecture coopère en mode écriture avec lesdits moyens d'adressage de ligne pour commander lesdits moyens de programmation de ladite ligne d'écriture segmentée.

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