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公开(公告)号：ITMI992372A1
公开(公告)日：2001-05-14
申请号：ITMI992372
申请日：1999-11-12
Applicant: ST MICROELECTRONICS SRL
Inventor： BEDARIDA LORENZO , BARTOLI SIMONE , SALI MAURO , RUSSO ANTONIO
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公开(公告)号：DE69514502D1
公开(公告)日：2000-02-17
申请号：DE69514502
申请日：1995-05-05
Applicant: ST MICROELECTRONICS SRL
Inventor： BEDARIDA LORENZO , CAMPARDO GIOVANNI , FUSILLO GIUSEPPE , SILVAGNI ANDREA
Abstract: A memory array (2) is divided, at the design stage, into a plurality of elementary sectors (4); depending on the specific application and the requirements of the user, the elementary sectors are grouped into composite sectors (34) of desired size and number; a correlating unit (31) memorizes the correlation between each composite sector and the elementary sectors; and, to address a composite sector, the relative address (32) is supplied to the correlating unit (31) which provides for addressing the elementary sectors (4) associated with the addressed composite sector on the basis of the memorized correlation table.
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公开(公告)号：ITMI992576D0
公开(公告)日：1999-12-13
申请号：ITMI992576
申请日：1999-12-13
Applicant: ST MICROELECTRONICS SRL
Inventor： BEDARIDA LORENZO , BARTOLI SIMONE , DIMA VINCENZO , GERACI ANTONINO
IPC: G05F3/24
Abstract: An output buffer device having first and second supply voltage references, the first voltage reference being lower in value than the second voltage reference. The output buffer device includes first and second complementary MOS transistors, which transistors are connected in series together between one of the supply voltage references and a further voltage reference, have gate terminals connected together and to an input terminal of this buffer device, and have drain terminals connected together and to an output terminal of the buffer device. Advantageously, the first transistor is connected to the first supply voltage reference. Furthermore, the output buffer device comprises at least one additional drive MOS transistor of the same type as the first MOS transistor and placed between the second supply voltage reference and the output terminal of the buffer device.
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Patent Agency Ranking
公开(公告)号：DE69928514D1
公开(公告)日：2005-12-29
申请号：DE69928514
申请日：1999-06-25
Applicant: ST MICROELECTRONICS SRL
Inventor： BEDARIDA LORENZO , DIMA VINCENZO , BRANI FRANCESCO , DEFENDI MARCO
Abstract: A circuit for reading a semiconductor memory device comprises at least one global circuit (1) for generating a global reference signal (RIFN) for a respective plurality of cell-reading circuits (SA1-SAn) disposed locally in the memory device. The circuit comprises at least one circuit (51-5an) for replicating the reference signal (RIFN) locally in order to generate a local reference signal (MAT11-MAT1n) to be supplied to at least one respective cell-reading circuit (SA1-SAn).
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公开(公告)号：IT1318013B1
公开(公告)日：2003-07-21
申请号：ITMI20001315
申请日：2000-06-13
Applicant: ST MICROELECTRONICS SRL
Inventor： LISI CARLO , BEDARIDA LORENZO , GERACI ANTONINO , DIMA VINCENZO
IPC: G11C16/28
Abstract: The present invention relates a circuit arrangement for the lowering of the threshold voltage of a diode configured transistor comprising a mirror transistor, a first transistor and a second transistor, said mirror transistor and said first transistor having in common the gate electrodes in a circuit node, said second transistor being connected in a transdiode configuration and placed between the gate electrode and the drain electrode of said first transistor, and a current source being connected to the gate electrode of said first transistor and to the drain electrode of said second transistor, characterized by comprising a third transistor which is configured to receive a switching signal at its gate electrode and is connected between the drain and the gate electrode of said first transistor.
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公开(公告)号：IT1314122B1
公开(公告)日：2002-12-04
申请号：ITMI992576
申请日：1999-12-13
Applicant: ST MICROELECTRONICS SRL
Inventor： DIMA VINCENZO , BEDARIDA LORENZO , GERACI ANTONINO , BARTOLI SIMONE
IPC: G05F3/24
Abstract: An output buffer device having first and second supply voltage references, the first voltage reference being lower in value than the second voltage reference. The output buffer device includes first and second complementary MOS transistors, which transistors are connected in series together between one of the supply voltage references and a further voltage reference, have gate terminals connected together and to an input terminal of this buffer device, and have drain terminals connected together and to an output terminal of the buffer device. Advantageously, the first transistor is connected to the first supply voltage reference. Furthermore, the output buffer device comprises at least one additional drive MOS transistor of the same type as the first MOS transistor and placed between the second supply voltage reference and the output terminal of the buffer device.
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公开(公告)号：DE69514502T2
公开(公告)日：2000-08-03
申请号：DE69514502
申请日：1995-05-05
Applicant: ST MICROELECTRONICS SRL
Inventor： BEDARIDA LORENZO , CAMPARDO GIOVANNI , FUSILLO GIUSEPPE , SILVAGNI ANDREA
Abstract: A memory array (2) is divided, at the design stage, into a plurality of elementary sectors (4); depending on the specific application and the requirements of the user, the elementary sectors are grouped into composite sectors (34) of desired size and number; a correlating unit (31) memorizes the correlation between each composite sector and the elementary sectors; and, to address a composite sector, the relative address (32) is supplied to the correlating unit (31) which provides for addressing the elementary sectors (4) associated with the addressed composite sector on the basis of the memorized correlation table.
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公开(公告)号：ITMI992372D0
公开(公告)日：1999-11-12
申请号：ITMI992372
申请日：1999-11-12
Applicant: ST MICROELECTRONICS SRL
Inventor： BEDARIDA LORENZO , BARTOLI SIMONE , SALI MAURO , RUSSO ANTONIO
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