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    21.
    发明专利
    未知

    公开(公告)号：DE69228807T2

    公开(公告)日：1999-08-12

    申请号：DE69228807

    申请日：1992-07-22

    Applicant: ST MICROELECTRONICS SRL

    Inventor： TOMASINI LUCIANO ,  CASTELLO RINALDO ,  ERRATICO PIETRO

    IPC: H04B1/58 ,  H04M1/58 ,  H04M1/76 ,  H04M1/00

    Abstract: A circuit (1) for synthesizing an impedance associated with a telephone subscriber's circuit (2) connected to a two-wire telephone line (3) is a positive feedback configuration comprising: a single precision resistance (R) connected serially to the line (3); at least one low-pass filter; and an amplifier (7) between the filter (8) and the resistance (R). This circuit (1) allows both the termination impedance and the balance impedance to be synthesized through a single external precision component.

    22.
    发明专利
    未知

    公开(公告)号：DE69224467D1

    公开(公告)日：1998-03-26

    申请号：DE69224467

    申请日：1992-09-15

    Applicant: ST MICROELECTRONICS SRL

    Inventor： TOMASINI LUCIANO ,  CASTELLO RINALDO

    IPC: H04M20060101 ,  H04M1/00 ,  H04M1/60 ,  H04M1/76 ,  H04M19/08

    Abstract: A circuit is described which comprises an operational amplifier A, two resistors R1, R2, connected between the telephone line L and the inputs of the amplifier, a capacitor C, which is charged by a first bipolar transistor P1 controlled by the amplifier via a first FET transistor M1, a second bipolar transistor P2 arranged in parallel with the connection of the first transistor P1 and the capacitor C, a second FET transistor M2, equal to the first and with "source" and "gate" terminals connected to the corresponding terminals of the first one, and two current generators CC1, CC2, connected to the "drain" terminals, respectively, of the first and the second FET transistor and to the bases, respectively, of the first and the second bipolar transistor P1, P2. The currents I1, I2 of the two generators and the other parameters of the circuit are such as to keep the first and the second bipolar transistor respectively conducting and inhibited, except in the case when the line voltage drops below a minimum predetermined value: in such case, the first and the second transistor respectively switch to inhibition and conduction. The circuit has a lower "voltage loss" than the known circuits.

    24.
    发明专利
    未知

    公开(公告)号：IT1316690B1

    公开(公告)日：2003-04-24

    申请号：ITMI20000393

    申请日：2000-02-29

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PISATI VALERIO ,  PORTALURI SALVATORE ,  CAZZANIGA MARCO ,  CASTELLO RINALDO

    IPC: H03F1/42 ,  H03H11/04

    Abstract: This invention relates to a circuit structure of the feedforward type with programmable zeroes, particularly for synthesizing time-continual filters. This structure comprises a pair of amplification cells (14,15) interconnected at at least one interconnection node (A) and connected between a first signal (Vin) input (IN) of a first cell (14) and an output terminal (U) of the second cell (15, each cell (14,15) comprising a pair of transistors (10,2;6,7) which have a conduction terminal in common and have the other conduction terminals coupled respectively to a first voltage reference (Vcc) through respective bias members (3,4;9,11). The structure further comprises a circuit leg (13) connecting a node (X) of the first cell (14) to the output terminal (U) and comprising a transistor (8) which has a control terminal connected to the node (X) of the first cell (14), a first conduction terminal connected to the output terminal (U), and a second conduction terminal coupled to a second voltage reference (GND) through a capacitor (Cc). Thus, a released "zero" can be introduced in the right semiplane of the pole-zero complex plane to improve the flattening of group gain.

    25.
    发明专利
    未知

    公开(公告)号：DE69529828D1

    公开(公告)日：2003-04-10

    申请号：DE69529828

    申请日：1995-11-30

    Applicant: ST MICROELECTRONICS SRL

    Inventor： TOMASINI LUCIANO ,  CASTELLO RINALDO ,  CLERICI GIANCARLO ,  BIETTI IVAN

    IPC: H03F1/08 ,  H03F1/00

    Abstract: An operational amplifier (5) with adjustable frequency compensation comprises a transconductance input stage (2) and an amplifier output stage (3) connected serially together between an input terminal (IN) and an output terminal (OUT) of the operational amplifier. At least one compensation block (6) is connected across the input and the output of said output stage (3), According to the invention, the compensation block (6) comprises a plurality (N) of charge storage elements (CCn) connected in parallel together and in series to a switch block (7) which selectively connects a sub-plurality (N') of said charge storage elements (CCn) across the input and the output of said output stage (3) on the basis of an external signal (SEL) of the amplifier (5).

    26.
    发明专利
    未知

    公开(公告)号：DE69623963D1

    公开(公告)日：2002-10-31

    申请号：DE69623963

    申请日：1996-10-11

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BASCHIROTTO ANDREA ,  NAGARI ANGELO ,  CASTELLO RINALDO

    IPC: H03F3/00 ,  H03F3/45 ,  H03H1/00

    Abstract: In switch-capacitor systems for extremely low supply voltage, employing fully differential switched op-amp, proper functioning of nMOS switches coupled to the inverting input node of an integrated stage capable of outputting a common mode control signal, is may possible by retaining the ground potential on the input node to prevent body effects on the threshold of nMOS switches by means of an auxiliary switched capacitor.

    27.
    发明专利
    未知

    公开(公告)号：ITMI20000393A1

    公开(公告)日：2001-08-29

    申请号：ITMI20000393

    申请日：2000-02-29

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CASTELLO RINALDO ,  PORTALURI SALVATORE ,  PISATI VALERIO ,  CAZZANIGA MARCO

    IPC: H03F1/42 ,  H03H11/04

    Abstract: This invention relates to a circuit structure of the feedforward type with programmable zeroes, particularly for synthesizing time-continual filters. This structure comprises a pair of amplification cells (14,15) interconnected at at least one interconnection node (A) and connected between a first signal (Vin) input (IN) of a first cell (14) and an output terminal (U) of the second cell (15, each cell (14,15) comprising a pair of transistors (10,2;6,7) which have a conduction terminal in common and have the other conduction terminals coupled respectively to a first voltage reference (Vcc) through respective bias members (3,4;9,11). The structure further comprises a circuit leg (13) connecting a node (X) of the first cell (14) to the output terminal (U) and comprising a transistor (8) which has a control terminal connected to the node (X) of the first cell (14), a first conduction terminal connected to the output terminal (U), and a second conduction terminal coupled to a second voltage reference (GND) through a capacitor (Cc). Thus, a released "zero" can be introduced in the right semiplane of the pole-zero complex plane to improve the flattening of group gain.

    28.
    发明专利
    未知

    公开(公告)号：ITVA990005A1

    公开(公告)日：2000-08-22

    申请号：ITVA990005

    申请日：1999-02-22

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MILANESE CARLO MARIA ,  CASTELLO RINALDO

    IPC: H03K3/3565 ,  H03K5/24

    Abstract: A comparator circuit includes a differential input stage, a second differential stage having a differential output, and an output stage transforming an output signal from the differential output of the second differential stage into an output signal having a logic level. The comparator further includes a common mode measuring stage. The common mode measuring stage includes a differential pair of input transistors and a differential pair of complementary transistors biased by respective current generators, and a current mirror summing the differential output currents of the two complementary transistors pairs into a single output current signal. A switching stage is controlled by the differential output nodes of the second differential stage. A common source node of the switch stage is coupled to the output of the common mode measuring stage and to the differential output nodes of the differential input stage.

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