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公开(公告)号：DE69419723T2
公开(公告)日：1999-12-02
申请号：DE69419723
申请日：1994-02-18
Applicant: ST MICROELECTRONICS SRL
Inventor： PASCUCCI LUIGI , GOLLA CARLA MARIA , MACCARRONE MARCO , OLIVO MARCO
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公开(公告)号：DE69318842T2
公开(公告)日：1998-12-24
申请号：DE69318842
申请日：1993-12-02
Applicant: ST MICROELECTRONICS SRL
Inventor： PASCUCCI LUIGI , GOLLA CARLA MARIA , MACCARRONE MARCO
Abstract: A memory line decoding driver (1) is so biased that the P channel pull-up transistor (6) biasing the final inverter (5) conducts a high current during the line address transient phase, for rapidly charging the input of the final inverter, and is turned on weakly during the static phase between one address phase and another, for reducing current consumption. For which purpose, a voltage modulating stage (18) alternatively connects the gate terminal of the pull-up transistor (6) to a capacitor (37), with which the charge is distributed, and to the supply (VPC).
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公开(公告)号：DE69739864D1
公开(公告)日：2010-06-10
申请号：DE69739864
申请日：1997-11-05
Applicant: ST MICROELECTRONICS SRL
Inventor： MICHELONI RINO , CAMPARDO GIOVANNI , FERRARIO DONATO , GOLLA CARLA MARIA
Abstract: A boosting circuit supplied by a first voltage level (Vcc) and a second voltage level (Gnd), and having an output line (13) capable of taking a third voltage level, characterized by comprising at least two distinct circuits (A1,11,A2,12) for generating said third voltage level, the at least two circuits selectively activatable for generating said third voltage level and selectively couplable to said output line (13).
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公开(公告)号：DE69615149T2
公开(公告)日：2002-07-04
申请号：DE69615149
申请日：1996-03-06
Applicant: ST MICROELECTRONICS SRL
Inventor： GOLLA CARLA MARIA , ZAMMATTIO MATTEO , ZANARDI STEFANO
IPC: G11C8/18 , H03K5/1534 , H03K3/011 , H03K3/355 , G11C8/00
Abstract: An address transition detection circuit (30) having a number of cells (1) supplied with respective address signals and output connected in a wired NOR configuration to generate a pulse signal (WN) on detecting transitions of their respective address signals. The pulse signal is supplied to a source stage for generating an address transition signal (ATDO) having a first and second switching edge on receiving the pulse signal. The source stage has a monostable stage (80) for generating an end-of-transition signal (ATDY) with a predetermined delay following reception of the pulse signal; and an output stage (35, 70) connected to the cells (1) and to the monostable stage (80), which generates the first switching edge of the address transition signal (ATDO) on receiving the pulse signal (WN), and the second switching edge on receiving the end-of-transition signal. The monostable stage (80) presents a compensating structure (40, 42, 44) for maintaining the delay in the switching of the end-of-transition signal (ATDY) stable alongside variations in temperature and supply voltage.
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公开(公告)号：DE69425367D1
公开(公告)日：2000-08-31
申请号：DE69425367
申请日：1994-04-19
Applicant: ST MICROELECTRONICS SRL
Inventor： PASCUCCI LUIGI , GOLLA CARLA MARIA , MACCARRONE MARCO
Abstract: A read circuit (1) comprising at least one array branch (2) connected to at least one bit line (5), and a reference branch (3) connected to a reference line (11). The array and reference branches each comprise a precharge circuit (4, 10) and load (8, 13, 15) interposed between the supply (7) and the bit line (5) and reference line (11) respectively. The reference load (13, 15) is so formed as to generate a reference current which, during evaluation, is twice the current supplied to the bit line (5). The reference line (11) is connected to an extra-current transistor (43) which is only turned on during equalization so that, during equalization, the selected bit line (5) is supplied with a high current approximating that supplied to the reference line (11). As such, if the cell to be read (6) is written, the output voltage of the array branch (2) is brought rapidly to its natural high value; whereas, if the cell to be read is erased, the output voltage may return to its low value when the extra-current transistor is turned off, thus permitting reading in advance.
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Patent Agency Ranking
公开(公告)号：DE69424860D1
公开(公告)日：2000-07-13
申请号：DE69424860
申请日：1994-02-18
Applicant: ST MICROELECTRONICS SRL
Inventor： PASCUCCI LUIGI , GOLLA CARLA MARIA
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公开(公告)号：DE69424523D1
公开(公告)日：2000-06-21
申请号：DE69424523
申请日：1994-02-18
Applicant: ST MICROELECTRONICS SRL
Inventor： PASCUCCI LUIGI , OLIVO MARCO , GOLLA CARLA MARIA
Abstract: A circuit (1) generates flexible timing permitting a slow or fast overall timing configuration, and two configurations of the precharge and detecting intervals by providing both with two (short or long) duration levels. For this purpose, the circuit (1) includes a variable, asymmetrical propagation line (5, 37) composed of a succession of elementary delay elements (6-8, 38, 40) enabled or disabled on the basis of memorized logic signals (TIMS, PCS, DETS), the state of which is determined when debugging the memory (100) in which the circuit (1) is implemented.
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公开(公告)号：DE69631518D1
公开(公告)日：2004-03-18
申请号：DE69631518
申请日：1996-04-30
Applicant: ST MICROELECTRONICS SRL
Inventor： MACCARRONE MARCO , MULATTI JACOPO , GOLLA CARLA MARIA
Abstract: A circuit (1) for generating biasing signals in reading of a redundant UPROM cell (2) incorporating at least one memory element (FC) of the EPROM or flash type and having a control terminal (GC) and a conduction terminal (DC) to be biased as well as MOS transistors (M1,M2) connecting said memory element (FC) with a reference low supply voltage (Vcc) comprises a voltage booster (3) for generating at output (U1) a first voltage signal (UGV) to be applied to the control terminal (GC) of the memory element (FC) and a limitation network (5) for said voltage signal (UGV) connected to the output (U1) of the voltage booster (3). There is also provided a circuit portion (10) for generating at output (U2) a second voltage signal (Vb) to be applied to the control terminal of one (M2) of the above mentioned transistors (M1,M2). This circuit portion (10) comprises a timing section (7) interlocked with the voltage booster (3) of a section (8) generating the second voltage signal (Vb).
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公开(公告)号：DE69421266T2
公开(公告)日：2000-05-18
申请号：DE69421266
申请日：1994-02-18
Applicant: ST MICROELECTRONICS SRL
Inventor： PASCUCCI LUIGI , PADOAN SILVIA , GOLLA CARLA MARIA , MACCARRONE MARCO , OLIVO MARCO
Abstract: The circuit (1) comprises a section (2) generating a pulse signal (ATD) for asynchronously enabling the read phases; a section (4) generating precharge (PC) and detecting (DET) signals of adjustable duration, for controlling data reading from the memory (104) and data supply to the output buffers (106); a section (5) generating a noise suppressing signal (N) for freezing the data in the output buffers during loading into the output circuits, and the duration of which is exactly equal to the propagation time of the data to the output circuits of the memory, as determined by propagating a data simulating signal (SP) in an out-like circuit (33); a section (6) generating a loading signal (L), the duration of which may be equal to that of the noise suppressing signal (N) or extended by an extension circuit (51) in the event the array presents slower elements which may thus be read; and a section (7) generating a circuit reset signal (END).
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公开(公告)号：DE69421266D1
公开(公告)日：1999-11-25
申请号：DE69421266
申请日：1994-02-18
Applicant: ST MICROELECTRONICS SRL
Inventor： PASCUCCI LUIGI , PADOAN SILVIA , GOLLA CARLA MARIA , MACCARRONE MARCO , OLIVO MARCO
Abstract: The circuit (1) comprises a section (2) generating a pulse signal (ATD) for asynchronously enabling the read phases; a section (4) generating precharge (PC) and detecting (DET) signals of adjustable duration, for controlling data reading from the memory (104) and data supply to the output buffers (106); a section (5) generating a noise suppressing signal (N) for freezing the data in the output buffers during loading into the output circuits, and the duration of which is exactly equal to the propagation time of the data to the output circuits of the memory, as determined by propagating a data simulating signal (SP) in an out-like circuit (33); a section (6) generating a loading signal (L), the duration of which may be equal to that of the noise suppressing signal (N) or extended by an extension circuit (51) in the event the array presents slower elements which may thus be read; and a section (7) generating a circuit reset signal (END).
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