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    21.
    发明专利
    未知

    公开(公告)号：IT1311441B1

    公开(公告)日：2002-03-12

    申请号：ITTO990994

    申请日：1999-11-16

    Applicant: ST MICROELECTRONICS SRL

    Inventor： KHOURI OSAMA ,  MICHELONI RINO ,  SACCO ANDREA ,  TORELLI GUIDO

    IPC: G11C5/14 ,  G11C11/56 ,  G11C16/30

    Abstract: The voltage generator comprises a negative feedback loop including a programmable voltage divider having a feedback node. The voltage divider comprises a programmable resistor disposed between the output of the voltage generator and the feedback node and having variable resistance. The programmable resistor includes a fixed resistor and a plurality of additional resistors arranged in series with each other and defining a plurality of intermediate nodes. The additional resistors may be selectively connected by means of switches disposed between the output of the voltage generator and a respective intermediate node so as to define an output voltage V0 programmable on the basis of command signals supplied to the switches.

    22.
    发明专利
    未知

    公开(公告)号：IT1311440B1

    公开(公告)日：2002-03-12

    申请号：ITTO990993

    申请日：1999-11-16

    Applicant: ST MICROELECTRONICS SRL

    Inventor： KHOURI OSAMA ,  MICHELONI RINO ,  SACCO ANDREA ,  TORELLI GUIDO

    IPC: G11C11/56 ,  G11C16/30

    Abstract: A voltage generator formed of a charge circuit and a discharge circuit having a common programmable voltage divider with variable resistance; the programmable voltage divider including a plurality of resistors arranged in series and selectively connectable to define alternatively a step-wise increasing program voltage and a fixed verify voltage. The charge circuit formed of a voltage regulator supplying at the output the precise voltage value determined by the programmable voltage divider, and the discharge circuit intervening when the output voltage must be switched in a controlled manner from a higher value to a lower value.

    24.
    发明专利
    未知

    公开(公告)号：ITTO990993A1

    公开(公告)日：2001-05-16

    申请号：ITTO990993

    申请日：1999-11-16

    Applicant: ST MICROELECTRONICS SRL

    Inventor： KHOURI OSAMA ,  MICHELONI RINO ,  SACCO ANDREA ,  TORELLI GUIDO

    IPC: G11C11/56 ,  G11C16/30

    Abstract: A voltage generator formed of a charge circuit and a discharge circuit having a common programmable voltage divider with variable resistance; the programmable voltage divider including a plurality of resistors arranged in series and selectively connectable to define alternatively a step-wise increasing program voltage and a fixed verify voltage. The charge circuit formed of a voltage regulator supplying at the output the precise voltage value determined by the programmable voltage divider, and the discharge circuit intervening when the output voltage must be switched in a controlled manner from a higher value to a lower value.

    26.
    发明专利
    未知

    公开(公告)号：IT1320666B1

    公开(公告)日：2003-12-10

    申请号：ITTO20000892

    申请日：2000-09-22

    Applicant: ST MICROELECTRONICS SRL

    Inventor： SACCO ANDREA ,  KHOURI OSAMA ,  MICHELONI RINO ,  TORELLI GUIDO

    IPC: G11C5/14 ,  G11C8/08 ,  G11C8/10 ,  G11C8/14 ,  G11C16/08

    Abstract: Described herein is a nonvolatile memory comprising a memory array organized according to global word lines and local word lines; a global row decoder; a local row decoder; a first supply stage for supplying the global row decoder; and a second supply stage for supplying the local row decoder; and a third supply stage for biasing the drain and source terminals of the memory cells of the memory array. Each of the supply stages comprises a respective resistive divider formed by a plurality of series-connected resistors, and a plurality of pass-gate CMOS switches each connected in parallel to a respective resistor. The nonvolatile memory further comprises a control circuit for controlling the pass-gate CMOS switches of the supply stages, and a switching circuit for selectively connecting the supply input of the control circuit to the output of the second supply stage during reading and programming of the memory, and to the output of the third supply stage during erasing of the memory.

    27.
    发明专利
    未知

    公开(公告)号：IT1319037B1

    公开(公告)日：2003-09-23

    申请号：ITMI20002337

    申请日：2000-10-27

    Applicant: ST MICROELECTRONICS SRL

    Inventor： KHOURI OSAMA ,  GREGORI STEFANO ,  PIERIN ANDREA ,  MICHELONI RINO ,  CORONINI SERGIO ,  TORELLI GUIDO

    IPC: G11C7/06 ,  G11C11/56 ,  G11C16/28 ,  G11C27/00

    Abstract: A circuit for reading a non-volatile memory cell has an output terminal for providing an output current, and a control terminal for receiving a voltage for controlling the output current. The reading circuit includes a feedback circuit which can be connected electrically to the output terminal and to the control terminal to generate the control voltage from a reference signal and from the output current. The feedback circuit also includes a current-amplification circuit having a first terminal for receiving a current-error signal derived from the reference signal and from the output current, and a second terminal for supplying an amplified current.

    28.
    发明专利
    未知

    公开(公告)号：IT1318158B1

    公开(公告)日：2003-07-23

    申请号：ITMI20001585

    申请日：2000-07-13

    Applicant: ST MICROELECTRONICS SRL

    Inventor： KHOURI OSAMA ,  PIERIN ANDREA ,  MICHELONI RINO ,  GREGORI STEFANO ,  TORELLI GUIDONO ,  SANGALLI MIRIAM

    IPC: G11C16/08

    Abstract: A circuit device for performing hierarchic row decoding in semiconductor memory devices of the non-volatile type, which memory devices include an array of memory cells with column-ordered sectors, wherein each sector has a respective group of local wordlines linked to a main wordline. The circuit device includes a main wordline driver provided at each main wordline, and a local decoder provided at each local wordline. This circuit device further comprises, for each main wordline, a dedicated path connected between the main wordline and the local decoders of the associated local wordlines and connected to an external terminal arranged to receive a read/program voltage, the dedicated path enabling transfer of the read/program voltage to the local decoders.

    29.
    发明专利
    未知

    公开(公告)号：ITMI20002337A1

    公开(公告)日：2002-04-29

    申请号：ITMI20002337

    申请日：2000-10-27

    Applicant: ST MICROELECTRONICS SRL

    Inventor： TORELLI GUIDO ,  MICHELONI RINO ,  KHOURI OSAMA ,  PIERIN ANDREA ,  GREGORI STEFANO ,  CORONINI SERGIO

    IPC: G11C7/06 ,  G11C11/56 ,  G11C16/28 ,  G11C27/00

    Abstract: A circuit for reading a non-volatile memory cell has an output terminal for providing an output current, and a control terminal for receiving a voltage for controlling the output current. The reading circuit includes a feedback circuit which can be connected electrically to the output terminal and to the control terminal to generate the control voltage from a reference signal and from the output current. The feedback circuit also includes a current-amplification circuit having a first terminal for receiving a current-error signal derived from the reference signal and from the output current, and a second terminal for supplying an amplified current.

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