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    23.
    发明专利
    未知

    公开(公告)号：DE69328253T2

    公开(公告)日：2000-09-14

    申请号：DE69328253

    申请日：1993-12-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MACCARRONE MARCO ,  OLIVO MARCO ,  GOLLA CARLA ,  PADOAN SILVIA

    IPC: G11C5/14 ,  G11C16/06 ,  G11C17/00 ,  G11C16/30

    Abstract: A voltage regulator for programming non-volatile memory cells, which comprises an amplifier stage (4) being powered between a first (VPP) and a second (GND) voltage reference and having a first input terminal connected to a resistive divider (2) of the first reference voltage (VPP) and an output terminal fed back to said input through a current mirror (3), and a source-follower transistor (MOUT) controlled by the output and connected to the cells through a programming line (VP). Also provided is a MOS transistor (MG2) which connects to ground the programming line (VP) and a corresponding resistive path (7) connected between the current mirror (3) and the second voltage reference (GND).

    25.
    发明专利
    未知

    公开(公告)号：DE69621020D1

    公开(公告)日：2002-06-06

    申请号：DE69621020

    申请日：1996-11-04

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MACCARRONE MARCO ,  ZAMMATTIO MATTEO ,  COMMODARO STEFANO

    IPC: G05F3/26 ,  G05F3/30

    Abstract: A band-gap reference voltage generator comprises an operational amplifier (2) comprising a first input and a second input, the first input being coupled to a first feedback network (4) and the second input being coupled to a second feedback network (6) both coupled to an output (7) of the operational amplifier providing a reference voltage, the first feedback network containing an emitter-base junction of first bipolar junction transistor means (Q1) and the second feedback network containing an emitter-base junction of second bipolar junction transistor means (Q2), and current supplying means (11) for supplying a bias current to the operational amplifier, the current supplying means being deactivatable in a substantially zero power consumption operating condition for turning the reference voltage generator off, characterized by comprising start-up circuit means (13) activated upon start-up of the reference voltage generator for a fixed, prescribed time interval for forcing a start-up current to flow through the first bipolar junction transistor means (Q1).

    26.
    发明专利
    未知

    公开(公告)号：DE69425367D1

    公开(公告)日：2000-08-31

    申请号：DE69425367

    申请日：1994-04-19

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI ,  GOLLA CARLA MARIA ,  MACCARRONE MARCO

    IPC: G11C17/00 ,  G11C16/06 ,  G11C16/24 ,  G11C16/28

    Abstract: A read circuit (1) comprising at least one array branch (2) connected to at least one bit line (5), and a reference branch (3) connected to a reference line (11). The array and reference branches each comprise a precharge circuit (4, 10) and load (8, 13, 15) interposed between the supply (7) and the bit line (5) and reference line (11) respectively. The reference load (13, 15) is so formed as to generate a reference current which, during evaluation, is twice the current supplied to the bit line (5). The reference line (11) is connected to an extra-current transistor (43) which is only turned on during equalization so that, during equalization, the selected bit line (5) is supplied with a high current approximating that supplied to the reference line (11). As such, if the cell to be read (6) is written, the output voltage of the array branch (2) is brought rapidly to its natural high value; whereas, if the cell to be read is erased, the output voltage may return to its low value when the extra-current transistor is turned off, thus permitting reading in advance.

    28.
    发明专利
    未知

    公开(公告)号：DE69419403T2

    公开(公告)日：1999-12-30

    申请号：DE69419403

    申请日：1994-02-18

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI ,  MACCARRONE MARCO ,  OLIVO MARCO

    IPC: G11C17/00 ,  G11C7/00 ,  G11C7/02 ,  G11C7/10 ,  G11C7/22 ,  G11C16/06 ,  G11C16/32

    Abstract: A load timing circuit (20) including an out-like circuit (21) identical to the output circuits of the memory, so as to present the same propagation time; a simulating signal source (34) for generating a data simulating signal (SP); a synchronizing network (30, 32) for detecting a predetermined switching edge of the data simulating signal (SP) and enabling (35) supply of the signal to the out-like circuit (21) and data supply to the output circuits of the memory; a combinatorial network (29, 30) for detecting propagation of the data simulating signal (SP) to the output of the out-like circuit and disabling the data simulating signal (SP); and a reset element (33) for resetting the timing circuit (20).

    29.
    发明专利
    未知

    公开(公告)号：DE69325587T2

    公开(公告)日：1999-12-23

    申请号：DE69325587

    申请日：1993-12-28

    Applicant: ST MICROELECTRONICS SRL

    Inventor： OLIVO MARCO ,  MACCARRONE MARCO

    IPC: G11C8/04 ,  G11C16/06 ,  H03K21/00 ,  G11C11/00

    Abstract: A count unit (1) for performing a number of count operations and wherein, instead of a counter for each count function, provision is made for one counter (8) and a number of registers (9, 10) equal in number to the count functions involved. The registers (9, 10) store the preceding count value and, when their content is to be incremented or in any way altered, load it into the counter (8) which provides for performing the required operation, at the end of which, the content of the counter is stored in the respective register. One (10) of the registers presents a second parallel input (ADDR) for externally loading an initial data which may be transferred to the other registers (9) via the counter (8).

    30.
    发明专利
    未知

    公开(公告)号：DE69324258D1

    公开(公告)日：1999-05-06

    申请号：DE69324258

    申请日：1993-12-28

    Applicant: ST MICROELECTRONICS SRL

    Inventor： OLIVO MARCO ,  MACCARRONE MARCO

    IPC: G11C17/00 ,  G11C16/04 ,  H03K21/38 ,  H03K19/21 ,  G11C16/06

    Abstract: An end-of-count detecting device (1) for nonvolatile memories, comprising a decoder (2) in the form of a wired OR structure of a number of transistors (3) of the same type, the gate terminals of which are fed with a count signal generated by a counter element (6) and having a predetermined end-of-count value to be detected. A load (7), which may be static, pseudo-dynamic or dynamic, is provided between the common node (4) of the decoder transistors (3) and a reference potential line (VDD); and the decoder output (4) formed by the common node assumes a different logic level according to whether or not the end-of-count value coded by the wired OR structure is reached. A number of wired OR structures may be arranged side by side with an array of transistors for detecting a number of end-of-count values of the same counter element.

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