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    23.
    发明专利
    未知

    公开(公告)号：DE69825060D1

    公开(公告)日：2004-08-19

    申请号：DE69825060

    申请日：1998-12-17

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BOLLATI GIACOMINO ,  ALINI ROBERTO ,  OTTINI DANIELE ,  BRUCCOLERI MELCHIORRE

    IPC: H03H11/04

    Abstract: A low pass filter with programmable equalization comprising at least a biquadratic cell (BIQUAD) and a converter of the input voltage (Vin) in a current (iz), proportional to the derivative of the input voltage, that is injected on a node of the biquadratic cell (BIQUAD) in order to introduce two real and opposed zeroes in the transfer function of the filter, is composed of two structurally similar circuits, functionally connected in cascade, each circuit being composed of a biquadratic cell and an input stage having two outputs injecting through a first current output (A) said current (iz) on an input capacitor (C1) of the respective biquadratic cell, by a direct coupling in a first of said two circuits and in an inverted manner in the second of said two circuits; a second voltage output (B) being coupled to an input of the respective biquadratic cell.

    24.
    发明专利
    未知

    公开(公告)号：DE69431656D1

    公开(公告)日：2002-12-12

    申请号：DE69431656

    申请日：1994-08-12

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BRIANTI FRANCESCO ,  ALINI ROBERTO ,  PISATI VALERIO ,  GADDUCCI PAOLO

    IPC: H03H11/04 ,  H03H1/00

    Abstract: A high-pass filter in particular for high-frequency applications and of the type comprising at least one input terminal (IN) and at least one output terminal (OUT) between which is defined a transfer function (FdT) and is inserted a biquadratic cell (18) incorporating a series of transconductance stages (2, 3, 4, 5) comprises a generator circuit (29) of variable currents (iK1, iK2) connected between a pair of stages (2, 3) of the biquadratic cell (18) and a voltage reference (GND). Said generator allows introduction of programmable zeroes in the transfer function (FdT) of the filter (20).

    26.
    发明专利
    未知

    公开(公告)号：DE69421071T2

    公开(公告)日：2000-04-20

    申请号：DE69421071

    申请日：1994-05-23

    Applicant: ST MICROELECTRONICS SRL

    Inventor： ZUFFADA MAURIZIO ,  GADDUCCI PAOLO ,  MOLONEY DAVID ,  ALINI ROBERTO

    IPC: G11B5/09 ,  G11B20/10

    Abstract: The device comprises a variable-gain input amplifier (21), a low-pass analog filter (22), a transversal analog filter (23) and two distinct and parallel sampling channels (24, 34) interposed between the transversal analog filter (23) and an RLL-NRZ decoder (25). The two sampling channels (24, 34) comprise, each of them, an analog-digital converter (26, 36) and a Viterbi detector (27, 37) arranged in succession one after the other and operating according to sampling sequences that alternate with one another.

    28.
    发明专利
    未知

    公开(公告)号：DE69327053T2

    公开(公告)日：2000-02-24

    申请号：DE69327053

    申请日：1993-09-21

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MOLONEY DAVID ,  GADDUCCI PAOLO ,  BETTI GIORGIO ,  ALINI ROBERTO

    IPC: G11B20/10 ,  G11B20/14 ,  H03M5/06 ,  H03M5/14

    Abstract: In a decoder for decoding a serial data stream, employing an extracted base clock signal, synchronous with an input, coded, serial data stream, a fractionary frequency clock signal for sampling a decoded output data stream and a second fractionary clock signal for synthesizing a pre-decoded value produced by a first combinative logic network within a second combinative logic network to produce a decoded value that is sent to an output sampling flip-flop, a pipelined operation is implemented by momentarily storing the bits that are processed in the second combinative logic network and by anticipating of two full cycles of the synchronous base clock the processing by said first combinative network of the n-number of bits handled by the decoder. Each one of the two combinative logic networks is permitted to complete its decoding process within a full clock cycle in advance of the raising front of the outpunt sampling clock signal. With the same fabrication technology and therefore with the same propagation delay of the two combinative logic networks, the maximum operating spead may be doubled. A limited number of additional components are required to implement the pipelined operation of the invention.

    29.
    发明专利
    未知

    公开(公告)号：DE69421071D1

    公开(公告)日：1999-11-11

    申请号：DE69421071

    申请日：1994-05-23

    Applicant: ST MICROELECTRONICS SRL

    Inventor： ZUFFADA MAURIZIO ,  GADDUCCI PAOLO ,  MOLONEY DAVID ,  ALINI ROBERTO

    IPC: G11B5/09 ,  G11B20/10

    Abstract: The device comprises a variable-gain input amplifier (21), a low-pass analog filter (22), a transversal analog filter (23) and two distinct and parallel sampling channels (24, 34) interposed between the transversal analog filter (23) and an RLL-NRZ decoder (25). The two sampling channels (24, 34) comprise, each of them, an analog-digital converter (26, 36) and a Viterbi detector (27, 37) arranged in succession one after the other and operating according to sampling sequences that alternate with one another.

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