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公开(公告)号：JP2588692B2
公开(公告)日：1997-03-05
申请号：JP2664295
申请日：1995-02-15
Applicant: ST MICROELECTRONICS SRL
Inventor： PASCUCCI LUIGI , OLIVO MARCO
IPC: G11C11/413 , G11C11/401 , G11C29/00 , G11C29/04
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公开(公告)号：JPH0896569A
公开(公告)日：1996-04-12
申请号：JP5038495
申请日：1995-02-16
Applicant: ST MICROELECTRONICS SRL
Inventor： PASCUCCI LUIGI , OLIVO MARCO , GOLLA CARLA MARIA
Abstract: PURPOSE: To obtain an internal timing method to a rewritable memory and a circuit thereof. CONSTITUTION: A circuit 1 generates slow or fast overall timing configuration and flexible timing enabling the two configuration of pre-charge and detection intervals by giving the levels of two short and long periods. For conduct the generation of the timing, variable asymmetric propagation lines 5, 37 consisting of a series of basic delay elements 6-8, 38, 40 bringing data to an enable or disenable state on the basis of logical signals TIMS, PCS, and DETS stored are contained in the circuit 1, and the state is determined when a memory 100 executed by the circuit is debugged.
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公开(公告)号：JPH0883494A
公开(公告)日：1996-03-26
申请号：JP5377795
申请日：1995-02-20
Applicant: ST MICROELECTRONICS SRL
Inventor： PASCUCCI LUIGI , GOLLA CARLA MARIA , MACCARRONE MARCO , OLIVO MARCO
Abstract: PURPOSE: To obtain a timer which can be constituted by a slow element excellent in noise characteristics. CONSTITUTION: This embodiment is a nonvolatile memory 100 comprising a data amplifier 106 and an output element 108 connecting with each other via a connection line 107. A noise suppression circuit 1 comprises networks 8, 18 for generating a noise suppression signal N which is synchronized completely with a signal L for controlling a data loading from the amplifier 106 to the output device 108. A very short lasting time period same as a switch time period of the output device 108 is given, and when the output device 108 is switched, the amplifier 106 is frozen, and data stored in the amplifier or an internal circuit of the memory 100 cannot be changed. An address amplifier 102 on address buses 101, 103 is blockaded according to the same signal.
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公开(公告)号：JPH0845289A
公开(公告)日：1996-02-16
申请号：JP5377695
申请日：1995-02-20
Applicant: ST MICROELECTRONICS SRL
Inventor： PASCUCCI LUIGI , MACCARRONE MARCO , OLIVO MARCO
Abstract: PURPOSE: To set a timing accurately while suppressing noise by loading a simulate signal to an output simulation circuit through a switch subjected to required control and resetting a simulate generation circuit in response to the variation of simulate signal. CONSTITUTION: Upon provision of a sync signal SYNC, a simulate signal SP is generated from the simulate signal generator 34 of delay FF and a load block signal SS makes a transition to L through a switch 35 opened by a load enable signal L before being loaded to an unblocked output simulation circuit 21. When the signal SP is inverted to 'L', output is inverted to H through a NAND gate 30 and an inverter 32 and the generator 34 is reset instantaneously through a monostable multivibrator 33. On the other hand, a signal SS is inverted to H and loading to the circuit 21 is blocked. According to the circuitry, loading of signal and blocking of loading are controlled accurately and the effect of noise due to housing is suppressed.
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公开(公告)号：JPH07326195A
公开(公告)日：1995-12-12
申请号：JP5656995
申请日：1995-02-21
Applicant: ST MICROELECTRONICS SRL
Inventor： GOLLA CARLA , PADOAN SILVIA , OLIVO MARCO
Abstract: PURPOSE: To prevent the occurrence of erase and change of contents of non- specified memory cells by providing a normally-open switch and a current generator to control a discharge current. CONSTITUTION: A memory cell 5 to be erased is specified. For performing the erasing, a programming voltage Vpp from a logical switch SW is connected to the cell to set a source line SRC a high voltage a normally-open switch 11 of control transistors M2 and M3 and an erase transistor M4. After completion of the erase stage, the line SRC has an erase voltage value higher than the high potential, which voltage is discharged to the ground. This causes a signal SL to be set at its high level, thus turning a switch I1 ON. This causes the voltage of the line SRC to be controlled by a current IS to continue slow discharging operation. In this way, since the discharging operation of the source line SRC is controlled to be gradually slow, the occurrence of erase/change of contents of the memory cells 5 other than the specified cell can be prevented.
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Patent Agency Ranking26.发明专利
公开(公告)号：JPH07272500A
公开(公告)日：1995-10-20
申请号：JP7186195
申请日：1995-03-29
Applicant: ST MICROELECTRONICS SRL
Inventor： PADOAN SILVIA , MACCARRONE MARCO , OLIVO MARCO
Abstract: PURPOSE: To improve and facilitate the measurement of the distribution of threshold voltage in a non-volatile memory-cell further. CONSTITUTION: A circuit device 1 for measuring the distribution of threshold voltage has a differential amplifier 3 connected to a circuit leg containing a memory-cell 2 and a reference circuit leg 4 and a circuit means unbalancing the values of currents flowing through each circuit leg. The circuit means comprises a variable current generator related to the reference circuit leg 4, the variable current generator is connected between a supply-voltage Vdd reference point and a ground-voltage GND reference point, and a current I2 as the function of supply voltage Vdd is generated in the reference circuit leg 4.
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公开(公告)号：JPH06325592A
公开(公告)日：1994-11-25
申请号：JP5878794
申请日：1994-03-29
Applicant: ST MICROELECTRONICS SRL
Inventor： OLIVO MARCO , PASCUCCI LUIGI
Abstract: PURPOSE: To unnecessitate a specified load circuit to program cells in a redundancy row by positioning at an intersection a line and a row of matrix itself and providing matrix consisting of memory cells. CONSTITUTION: A load circuit 3 for programming is connected to a common drain of transistors MS and MSR of each bucket 1. The circuit 3 consists of P channel MOS type transistor MP1, its drain is connected to the common drain of the transistors MS and MSR, its source is connected to programming voltage VP and its gate is connected to an input of a circuit 4 which has a NAND logic function. The circuit 4 is provided with a P channel MOS type load transistor M41, its source and drain are respectively connected to the voltage VP and a gate of the MP1 and make them ground electric potential. A drain of a transistor M42 is connected to a drain of the transistor M41, a drain of a transistor M43 is connected to its source, the source is ground electric potential and signals YMO to YM7 are given here. Thus, a signal DIN to program is acquired.
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公开(公告)号：DE69319886T2
公开(公告)日：1999-03-18
申请号：DE69319886
申请日：1993-03-31
Applicant: SGS THOMSON MICROELECTRONICS
Inventor： OLIVO MARCO , PASCUCCI LUIGI
Abstract: There is described a semiconductor memory comprising a matrix of lines and columns of memory cells, wherein the columns (BL) are grouped together in sectors, each sector representing the portion of the matrix itself related to a data input/output line. Each sector is in turn divided into packets (1) of columns, and there are redundancy columns (BLR) suitable for replacing a matrix column (BL) containing defective memory cells. Each of the redundancy columns (BLR) is included in a respective packet (1). The memory also comprises control circuits (5,6,7) to execute the abovementioned replacement.
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公开(公告)号：DE69029968T2
公开(公告)日：1997-06-05
申请号：DE69029968
申请日：1990-11-19
Applicant: SGS THOMSON MICROELECTRONICS
Inventor： PASCUCCI LUIGI , OLIVO MARCO
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公开(公告)号：DE69026946T2
公开(公告)日：1996-09-05
申请号：DE69026946
申请日：1990-11-19
Applicant: SGS THOMSON MICROELECTRONICS
Inventor： PASCUCCI LUIGI , OLIVO MARCO
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