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    Phase-change memory device and manufacturing process thereof
    25.
    发明公开
    Phase-change memory device and manufacturing process thereof 有权
    法新社 - 佛罗伦萨

    公开(公告)号：EP1684352A1

    公开(公告)日：2006-07-26

    申请号：EP05425024.6

    申请日：2005-01-21

    Applicant: STMicroelectronics S.r.l.

    Inventor： Zuliani, Paola ,  Pellizzer, Fabio ,  Bez, Roberto

    IPC: H01L27/24 ,  H01L45/00 ,  G11C11/34

    CPC classification number: H01L27/2436 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144

    Abstract: Phase-change memory device, wherein memory cells (2) are arranged in rows (7) and columns (6) and form a memory array. The memory cells (2) are formed by a selection device (4) of an MOS type and by a phase-change region (3) connected to the selection device. The selection device (4) is formed by a first conductive region (32) and a second conductive region (33), which extend in a substrate (31) of semiconductor material and are spaced from one another via a channel region (34), and by an isolated control region (36) connected to a respective row (7) and overlying the channel region (34). The first conductive region (32) is connected to a connection line (42) extending parallel to the rows, the second conductive region (33) is connected to the phase-change region (46), and the phase-change region is connected to a respective column (6). The first connection line (42) is a metal interconnection line and is connected to the first conductive region (32) via a source-contact region (40) made as point contact and distinct from the first connection line (42).

    Abstract translation: 相变存储器件，其中存储器单元（2）以行（7）和列（6）排列并形成存储器阵列。 存储单元（2）由MOS型的选择装置（4）和连接到选择装置的相变区域（3）形成。 选择装置（4）由在半导体材料的衬底（31）中延伸并且经由沟道区（34）彼此间隔开的第一导电区域（32）和第二导电区域（33）形成， 以及连接到相应行（7）并且覆盖通道区域（34）的隔离控制区域（36）。 第一导电区域（32）连接到与行平行延伸的连接线（42），第二导电区域（33）连接到相变区域（46），相变区域连接到 相应的列（6）。 第一连接线（42）是金属互连线，并且经由源点接触区域（40）与第一导电区域（32）连接，源极接触区域（40）形成为与第一连接线（42）不同的点接触。

    Process for manufacturing a memory device, in particular a phase change memory, including a silicidation step
    26.
    发明公开
    Process for manufacturing a memory device, in particular a phase change memory, including a silicidation step 有权
    一种用于制造存储器件的方法，特别是相变存储器，所述方法包括硅化

    公开(公告)号：EP1439579A9

    公开(公告)日：2005-02-09

    申请号：EP03425017.5

    申请日：2003-01-15

    Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

    Inventor： Pellizzer, Fabio ,  Bez, Roberto ,  Tosi, Marina

    IPC: H01L21/8234 ,  H01L21/8239

    CPC classification number: H01L21/823835 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144

    Abstract: A process wherein an insulating region (13) is formed in a body at least around an array portion (51) of a semiconductor body (10); a gate region (16) of semiconductor material is formed on top of a circuitry portion (51) of the semiconductor body (10); a first silicide protection mask (52) is formed on top of the array portion; the gate region (16) and the active areas (43) of the circuitry portion (51) are silicided and the first silicide protection mask (52) is removed. The first silicide protection mask (52) is of polysilicon and is formed simultaneously with the gate region (16). A second silicide protection mask (53) of dielectric material covering the first silicide protection mask (52) is formed before silicidation of the gate region (16). The second silicide protection mask (53) is formed simultaneously with spacers (41) formed laterally to the gate region (16).

    Process for manufactoring integrated resistive elements with silicidation protection
    27.
    发明公开
    Process for manufactoring integrated resistive elements with silicidation protection 审中-公开
    Verfahren zur Herstellung integrierter Widerstandselemente mit Silizidationsschutz

    公开(公告)号：EP1403909A1

    公开(公告)日：2004-03-31

    申请号：EP02425586.1

    申请日：2002-09-30

    Applicant: STMicroelectronics S.r.l.

    Inventor： Grossi, Alessandro ,  Bez, Roberto ,  Servalli, Giorgio

    IPC: H01L21/02 ,  H01L27/08

    CPC classification number: H01L28/20 ,  H01L27/0802

    Abstract: A process for the fabrication of integrated resistive elements with protection from silicidation envisages the steps of: delimiting, in a semiconductor wafer (10), at least one active area (15); and forming, in the active area (15) at least one resistive region (21) having a pre-determined resistivity. Prior to forming the resistive region (21), on top of the active area (15) a delimitation structure (20) for delimiting the resistive region (21) is obtained, and, subsequently, protective elements (25), which extend within the delimitation structure (20) and coat the resistive region (21), are obtained.

    Abstract translation: 集成电阻器通过在半导体晶片（10）中限定至少一个有效区域来制造; 以及在所述有源区域中形成具有预设电阻率的电阻区域。 在有源区域的顶部，形成用于限定电阻区域的定界结构。 获得了在限定结构内延伸并覆盖电阻区域的保护元件。

    Phase change memory cell and manufacturing method thereof using minitrenches
    28.
    发明公开
    Phase change memory cell and manufacturing method thereof using minitrenches 有权
    Phasenwechsel-Speicherzelle sowie deren Herstellungsverfahren手套Minigräben

    公开(公告)号：EP1339110A1

    公开(公告)日：2003-08-27

    申请号：EP02425087.0

    申请日：2002-02-20

    Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

    Inventor： Bez, Roberto ,  Pellizzer, Fabio ,  Tosi, Marina ,  Zonca, Romina

    IPC: H01L45/00 ,  H01L27/24

    CPC classification number: H01L45/06 ,  H01L27/2445 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691

    Abstract: The phase change memory cell (5) is formed by a resistive element (22) and by a memory region (38) of a phase change material. The resistive element has a first thin portion having a first sublithographic dimension in a first direction (Y) ; and the memory region (38) has a second thin portion (38a) having a second sublithographic dimension in a second direction (X) transverse to the first dimension. The first thin portion (22) and the second thin portion (38a) are in direct electrical contact and define a contact area (58) of sublithographic extension. The second thin portion (38a) is delimited laterally by oxide spacer portions (55a) surrounded by a mold layer (49) which defines a lithographic opening (51). The spacer portions (55a) are formed after forming the lithographic opening, by a spacer formation technique.

    Abstract translation: 相变存储单元（5）由电阻元件（22）和相变材料的存储区域（38）形成。 电阻元件具有在第一方向（Y）上具有第一亚光刻尺寸的第一薄部分。 并且所述存储区域（38）具有在横向于所述第一尺寸的第二方向（X）上具有第二亚光刻尺寸的第二薄部分（38a）。 第一薄部分（22）和第二薄部分（38a）直接电接触并限定亚光刻延伸部分的接触区域（58）。 第二薄部分（38a）由限定光刻开口（51）的模制层（49）围绕的氧化物间隔部分（55a）横向限定。 间隔物部分（55a）通过间隔物形成技术在形成光刻开口之后形成。

    Nonvolatile memory cell with high programming efficiency
    29.
    发明公开
    Nonvolatile memory cell with high programming efficiency 有权
    NichtflüchtigeSpeicherzelle mit hoher Programmierungsleistung

    公开(公告)号：EP1178540A1

    公开(公告)日：2002-02-06

    申请号：EP00830546.8

    申请日：2000-07-31

    Applicant: STMicroelectronics S.r.l.

    Inventor： Esseni, David ,  Selmi, Luca ,  Bez, Roberto ,  Modelli, Alberto

    IPC: H01L29/788 ,  H01L27/115

    CPC classification number: H01L29/66825 ,  G11C16/0416 ,  H01L27/11521 ,  H01L29/7885

    Abstract: The memory cell (1) is formed in a body (3) of a P-type semiconductor material forming a channel region (25) and housing N-type drain and source regions (15, 12) at two opposite sides of the channel region (25). A floating gate region (5) extends above the channel region (25). A P-type charge injection region (18) extends in the body (3) contiguously to the drain region (15), at least in part between the channel region (25) and the drain region (15). An N-type base region (21) extends between the drain region (15), the charge injection region (18), and the channel region (25). The charge injection region (18) and the drain region (15) are biased by special contact regions (19, 16) so as to forward bias the PN junction formed by the charge injection region (18) and the base region (21). The holes thus generated in the charge injection region (18) are directly injected through the base region (21) into the body (3), where they generate, by impact, electrons that are injected towards the floating gate region (5).

    Abstract translation: 存储单元（1）形成在形成沟道区域（25）的P型半导体材料的主体（3）中，并且在沟道区域的两个相对侧容纳N型漏极和源极区域（15,12） （25）。 浮动栅极区域（5）在沟道区域（25）的上方延伸。 P型电荷注入区域（18）至少部分地在沟道区域（25）和漏极区域（15）之间连续延伸到漏极区域（15）。 N型基极区域（21）在漏极区域（15），电荷注入区域（18）和沟道区域（25）之间延伸。 电荷注入区域（18）和漏极区域（15）被特殊接触区域（19,16）偏置，以便对由电荷注入区域（18）和基极区域（21）形成的PN结进行正向偏压。 这样在电荷注入区域（18）中产生的空穴通过基极区域（21）直接注入到体（3）中，在那里它们通过冲击产生被注入到浮动栅极区域（5）的电子。

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