公开(公告)号：JP2004172620A

公开(公告)日：2004-06-17

申请号：JP2003385281

申请日：2003-11-14

Applicant: United Microelectronics Corp ,  聯華電子股▲ふん▼有限公司

Inventor： RO KATETSU ,  RI DAII ,  WANG KUANG-CHIH ,  YANG MING-SHENG

IPC: H01L23/522 ,  H01L21/027 ,  H01L21/768 ,  H01L23/52

Abstract: PROBLEM TO BE SOLVED: To provide a high-performance integrated circuit, particularly an integrated circuit with air gaps that fully supports metal interconnection, for the solution of problems associated with the prior art. SOLUTION: The structure of the integrated circuit comprises: a substrate 11 with an underlayer 12; the first metallic pattern 13 formed in the underlayer; the second metallic layer 17 formed above the first metallic pattern; a supporting structure with an isotropic-etched dielectric layer 14 that supports the second metallic pattern formed between the first metallic pattern and the second metallic pattern; and multiple air gaps 18a formed in a gap in the second metallic pattern that is composed of a capping layer 19. COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2003179140A

公开(公告)日：2003-06-27

申请号：JP2002358268

申请日：2002-12-10

Applicant: UNITED MICROELECTRONICS CORP

Inventor： YEW TRI-RUNG ,  RYU MOSHO ,  RO KATETSU ,  SUN SHIH-WEI

IPC: H01L21/3065 ,  H01L21/768

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing an integrated circuit by a double-damascene process which exhibits a wide process flexibility and can be easily adapted in mass-production process. SOLUTION: After an etch stop layer 54 is patterned for forming an opening 72 corresponding to a pattern in a connection which is formed on the first level of a two-level connection structure, an intermetallic dielectric layer 58 is provided on it and a photoresist mask 62 is provided on it. Openings 64 and 66 of the mask 62 correspond to the wiring pattern provided on the second level of the connection structure and a dielectric layer 58 is partially exposed from them. The dielectric layer 58 is etched and the etching is advanced in such a way that an opening 68 is produced in the exposed part of the stop layer 54 from the opening 72 of the interlayer dielectric layer 52. In other words, openings for both of the wiring on the second level and the connection on the first level are demarcated by a single etching process. Further, the opening 72 of the stop layer is tapered with its upper diameter being larger than its lower diameter. COPYRIGHT: (C)2003,JPO

公开(公告)号：JP2001007107A

公开(公告)日：2001-01-12

申请号：JP16542499

申请日：1999-06-11

Applicant: UNITED MICROELECTRONICS CORP

Inventor： CHIN GAKUCHU ,  KO EKIMEI ,  YO MEISEI ,  WU JUAN-YUAN ,  RO KATETSU

IPC: H01L23/52 ,  H01L21/3205

Abstract: PROBLEM TO BE SOLVED: To prevent the electrical resistance of wiring from increasing by providing a dummy pattern which protects from excessive erosion caused by CMP(chemical mechanical polishing) within a high-density array. SOLUTION: An opening 200a and a groove 200b are formed in a dielectric layer 204 on a semiconductor substrate 202, and another opening 208 is simultaneously formed in the outside of the groove 200b when the opening 200a and the groove 200b are formed. Then, when metal is to be filled into the openings 200a and 200b, the metal is filled also into the opening 208, thus wiring 214a and 214b in a high-density array 206 and a metal line 216 in a dummy pattern 210 are formed. In this manner, the metal line 216 is allowed to function as a buffer material for preventing the wiring 214a and 214b from being excessively eroded.

公开(公告)号：JP2000306867A

公开(公告)日：2000-11-02

申请号：JP11076999

申请日：1999-04-19

Applicant: UNITED MICROELECTRONICS CORP

Inventor： CHIN GAKUCHU ,  YU KEISEI ,  WU JUAN-YUAN ,  RO KATETSU

IPC: H01L21/768 ,  H01L21/288 ,  H01L21/304 ,  H01L21/3063

Abstract: PROBLEM TO BE SOLVED: To provide a method for increasing uniformity of mechanochemical polishing, using an electrolytic conductor layer. SOLUTION: In this method for increasing uniformity of mechanochemical polishing using an electrolytic conductor layer, upon formation of a conductor layer, the conductor layer is processed in an electrolytic process to decrease the thickness of the conductor layer and remove uneven parts on its surface, and thereafter the surface of the conductor layer is polished in a mechanochemical polishing process. The thickness of the conductor layer is decreased by the electrolytic process, thereby shortening the time necessary by the subsequent mechanochemical polishing process. At the same time, since charges 34 are concentrated on projected parts on the surface of the conductor layer, the electrolysis rate of the projected parts becomes faster than that of recessed parts thereon, unevenness on the conductor layer surface is improved. When the conductor layer is formed through electroplating, its efficiency is further improved.

公开(公告)号：JP2000036541A

公开(公告)日：2000-02-02

申请号：JP28135498

申请日：1998-10-02

Applicant: UNITED MICROELECTRONICS CORP

Inventor： SHA CHOKEI ,  WOO SHUNGEN ,  RO KATETSU

IPC: H01L21/768 ,  H01L21/28 ,  H01L21/285

Abstract: PROBLEM TO BE SOLVED: To prevent a deviation or the like of a pattern in a photolithography or the like by vapor-depositing an intermetallic dielectric layer, patterning a via hole, then forming a titanium layer on the dielectric layer to connect a first aluminum layer formed in the hole, and forming a second aluminum layer on the titanium layer. SOLUTION: A first metal layer 202 is formed on a substrate 200, and then an intermetallic dielectric layer 204 is vapor deposited on the substrate 200 via a CVD. Then, the layer 204 is etched by using a photoresist pattern until a surface of the layer 202 is exposed to form a via hole 208. a second aluminum layer 211 is vapor deposited in the hole 208, and an aluminum via hole 213 is formed. Thereafter, a titanium layer 214 is formed on the layer 204 and the hole 213 by a physical vapor deposition method. A second aluminum layer 216 is formed on the layer 214 by using a physical vapor deposition method.

公开(公告)号：JP2945646B2

公开(公告)日：1999-09-06

申请号：JP1051198

申请日：1998-01-22

Applicant: UNITED MICROELECTRONICS CORP

Inventor： YEW TRI-RUNG ,  RO KATETSU ,  SUN SHIH-WEI ,  SHIH HSUEH-HAO

IPC: C23C16/04 ,  C23C16/24 ,  H01L21/02 ,  H01L21/205 ,  H01L21/285 ,  H01L21/8242 ,  H01L27/108

公开(公告)号：JPH11186200A

公开(公告)日：1999-07-09

申请号：JP34664497

申请日：1997-12-16

Applicant: UNITED MICROELECTRONICS CORP

Inventor： YO MEISEI ,  WU JUAN-YUAN ,  RO KATETSU ,  SUN SHIH-WEI

IPC: H01L21/304 ,  C09K3/14 ,  H01L21/321

Abstract: PROBLEM TO BE SOLVED: To enable CMP process of tungsten with the same polishing pad and the same polishing station, by polishing a dielectric layer after polishing process of a metal layer, and setting pH values of first slurry mixed solution and second slurry mixed solution in the respective specified ranges. SOLUTION: In a process, a chemically/mechanically polishing method is contained, a dielectric layer is formed, and at least one via of a through hole is formed in the dielectric layer. A tungsten layer is formed in the via and on the dielectric layer. In order to eliminate the tungsten layer form the dielectric layer, first slurry 42 having oxidizing component whose pH value is about 2-4 is used, and first chemically/mechanically polishing process is performed. By using second slurry whose pH value is about 2-4, second chemically/ mechanically polishing processing is performed, and the dielectric layer is polished.

公开(公告)号：JPH11163260A

公开(公告)日：1999-06-18

申请号：JP30673497

申请日：1997-11-10

Applicant: UNITED MICROELECTRONICS CORP

Inventor： YEW TRI-RUNG ,  RO KATETSU ,  SUN SHIH-WEI

IPC: H01L27/04 ,  H01L21/822

Abstract: PROBLEM TO BE SOLVED: To increase the charge conservation capability of an integrated-circuit capacitor, which can be utilized in a memory, and to provided increased conservation capability even though the manufacturing cost is decreased at the same time. SOLUTION: This method is for forming the increased capacitance for the charge conservation structure of an integrated-circuit device and includes the following processes. In a first process, access circuits 16 and 18, which control access to the electrode of the charge conservation structure through an electrode contact 22, are formed on a substrate 10. In a second process, a first conducting layer 36 is formed on a substrate 10 under the contact state with the electrode contact 22. In a third process, a dielectric material layer 42 is formed on the first conducting layer 36. In a fourth process, the layer of polysilicon particles 40 is formed on the dielectric material layer 42, and a non-covered part is made to remain between the particles. In a fifth process, these exposed parts of the dielectric material layer 42 are selectively removed, and column bodies 42 of the dielectric material are formed with an interval which is provided on these columnar bodies 42. In a sixth process, a second conducting layer 44 is formed on these columnar bodies 42. In a seventh process, a capacitor layer 44 is formed on these columnar bodies 42. In a eigth process, a capacitor dielectric layer 46 is formed on the second dielectric layer 44. In a last process, a third dielectric layer 50 is formed on the capacitor dielectric layer 46.

公开(公告)号：JPH11121718A

公开(公告)日：1999-04-30

申请号：JP1051198

申请日：1998-01-22

Applicant: UNITED MICROELECTRONICS CORP

Inventor： YEW TRI-RUNG ,  RO KATETSU ,  SUN SHIH-WEI ,  SHIH HSUEH-HAO

IPC: C23C16/04 ,  C23C16/24 ,  H01L21/02 ,  H01L21/205 ,  H01L21/285 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To obtain the capacitor storage node of an integrated circuit by a method wherein the title semispherical silicon crystalline particle structure is selectively formed by the chemical vapor phase synthetic process producing a by-product using chlorosilane as a precursor. SOLUTION: A substrate 20 having silicon oxide layers 24 and a contact hole 22 passing through them 24 is prepared while the contact hole 22 is filled up with polycystalline silicon so as to form a contact plug. After the formation of a polycrystalline silicon layer 26 on the contact hole 22 and the silicon oxide layers 24, the polycrystalline silicon layer 26 is patterned to form a lower part electrode. Next, silicon crystalline particles are grown using chlorosilane as a precursor. At this time the nuclear growth of silicon on the polycrystalline silicon layer 26 rapidly advances while the etching away speed of silicon by HCl is slower than that of HSG-Si structure but the silicon nuclear growth on the silicon oxide layers 24 takes a long time thereby raking the formation of the HSG-Si structure selectable.