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    Multichip dynamic range enhancement (DRE) audio processing methods and apparatuses
    21.
    发明授权
    Multichip dynamic range enhancement (DRE) audio processing methods and apparatuses 有权
    多芯片动态范围增强（DRE）音频处理方法和装置

    公开(公告)号：US09584911B2

    公开(公告)日：2017-02-28

    申请号：US14975015

    申请日：2015-12-18

    Applicant: Cirrus Logic, Inc.

    Inventor： Tejasvi Das ,  John L. Melanson

    IPC: H03M1/00 ,  H04R3/04 ,  H03G7/00 ,  H03G9/00 ,  H03M1/12 ,  H04L1/20 ,  H04L27/26

    CPC classification number: H04R3/04 ,  G10L19/167 ,  G10L21/0324 ,  H03G7/007 ,  H03G9/005 ,  H03M1/00 ,  H03M1/12 ,  H03M1/1225 ,  H03M1/18 ,  H03M2201/4135 ,  H04L1/20 ,  H04L27/2647 ,  H04R2430/01 ,  H04R2430/03

    Abstract: In accordance with embodiments of the present disclosure, a multichip circuit for processing audio signals having dynamic range enhancement information over two or more integrated circuits may include a host integrated circuit and a client integrated circuit. The host integrated circuit may be configured to determine a dynamic range enhancement gain for a digital audio input signal, process the digital audio input signal in accordance with the dynamic range enhancement gain, and transmit audio data based on the processed digital audio input signal. The client integrated circuit may be coupled to the host integrated circuit and may be configured to receive the audio data and wherein the client integrated circuit is provided with the dynamic range enhancement gain and the client integrated circuit is configured to process the audio data with the dynamic range enhancement gain.

    Abstract translation: 根据本公开的实施例，用于处理在两个或多个集成电路上具有动态范围增强信息的音频信号的多芯片电路可以包括主机集成电路和客户端集成电路。 主机集成电路可以被配置为确定用于数字音频输入信号的动态范围增强增益，根据动态范围增强增益处理数字音频输入信号，并且基于处理的数字音频输入信号发送音频数据。 客户端集成电路可以耦合到主机集成电路，并且可以被配置为接收音频数据，并且其中向客户端集成电路提供动态范围增强增益，并且客户端集成电路被配置为使用动态范围处理音频数据 范围增强增益。

    MULTICHIP DYNAMIC RANGE ENHANCEMENT (DRE) AUDIO PROCESSING METHODS AND APPARATUSES
    22.
    发明申请
    MULTICHIP DYNAMIC RANGE ENHANCEMENT (DRE) AUDIO PROCESSING METHODS AND APPARATUSES 有权
    多媒体动态范围增强（DRE）音频处理方法和设备

    公开(公告)号：US20160286310A1

    公开(公告)日：2016-09-29

    申请号：US14975015

    申请日：2015-12-18

    Applicant: Cirrus Logic, Inc.

    Inventor： Tejasvi Das ,  John L. Melanson

    IPC: H04R3/04

    CPC classification number: H04R3/04 ,  G10L19/167 ,  G10L21/0324 ,  H03G7/007 ,  H03G9/005 ,  H03M1/00 ,  H03M1/12 ,  H03M1/1225 ,  H03M1/18 ,  H03M2201/4135 ,  H04L1/20 ,  H04L27/2647 ,  H04R2430/01 ,  H04R2430/03

    Abstract: In accordance with embodiments of the present disclosure, a multichip circuit for processing audio signals having dynamic range enhancement information over two or more integrated circuits may include a host integrated circuit and a client integrated circuit. The host integrated circuit may be configured to determine a dynamic range enhancement gain for a digital audio input signal, process the digital audio input signal in accordance with the dynamic range enhancement gain, and transmit audio data based on the processed digital audio input signal. The client integrated circuit may be coupled to the host integrated circuit and may be configured to receive the audio data and wherein the client integrated circuit is provided with the dynamic range enhancement gain and the client integrated circuit is configured to process the audio data with the dynamic range enhancement gain.

    Abstract translation: 根据本公开的实施例，用于处理在两个或多个集成电路上具有动态范围增强信息的音频信号的多芯片电路可以包括主机集成电路和客户端集成电路。 主机集成电路可以被配置为确定用于数字音频输入信号的动态范围增强增益，根据动态范围增强增益处理数字音频输入信号，并且基于处理的数字音频输入信号发送音频数据。 客户端集成电路可以耦合到主机集成电路，并且可以被配置为接收音频数据，并且其中向客户端集成电路提供动态范围增强增益，并且客户端集成电路被配置为使用动态范围处理音频数据 范围增强增益。

    Method and system for translating digital signal sampled at variable frequency
    23.
    发明授权
    Method and system for translating digital signal sampled at variable frequency 失效
    用于转换可变频率采样的数字信号的方法和系统

    公开(公告)号：US4568912A

    公开(公告)日：1986-02-04

    申请号：US475406

    申请日：1983-03-15

    Applicant: Masatsugu Kitamura ,  Mitsuaki Tanaka

    Inventor： Masatsugu Kitamura ,  Mitsuaki Tanaka

    IPC: H03M1/00 ,  H04B12/02

    CPC classification number: H03M1/00 ,  H03M2201/02 ,  H03M2201/162 ,  H03M2201/196 ,  H03M2201/198 ,  H03M2201/3115 ,  H03M2201/3168 ,  H03M2201/4135 ,  H03M2201/415 ,  H03M2201/4225 ,  H03M2201/4233 ,  H03M2201/4262 ,  H03M2201/532 ,  H03M2201/534 ,  H03M2201/648 ,  H03M2201/838

    Abstract: In a data compression system, a digital signal comprising a series of digital samples and a sampling datum associated with each digital sample is received by a decoder. The sampling datum indicates the sampling interval of the associated digital sample. The decoder includes a microcomputer for storing the digital signal into a memory (M2) and reading each digital sample and the associated sampling datum. The digital sample is divided by the sampling datum to derive a quotient which indicates the slope of the signal to be recovered. The quotient is integrated by an integrator (6b) to provide interpolation between successive sampling points, so that the original signal is approximated by a plurality of line segments.

    Abstract translation: 在数据压缩系统中，由解码器接收包括一系列数字样本和与每个数字样本相关联的采样数据的数字信号。 采样数据表示相关数字采样的采样间隔。 解码器包括用于将数字信号存储到存储器（M2）中并读取每个数字样本和相关联的采样数据的微型计算机。 数字样本被采样数据除以导出指示要恢复的信号的斜率的商。 积分器（6b）对商进行积分，以在连续采样点之间提供内插，使原始信号由多个线段近似。

    Multi stage resistive ladder network having extra stages for trimming
    25.
    发明授权
    Multi stage resistive ladder network having extra stages for trimming 失效
    多级电阻梯形网络具有额外的修整阶段

    公开(公告)号：US4338590A

    公开(公告)日：1982-07-06

    申请号：US110135

    申请日：1980-01-07

    Applicant: Joseph J. Connolly, Jr. ,  James B. Cecil

    Inventor： Joseph J. Connolly, Jr. ,  James B. Cecil

    IPC: H03M1/00 ,  H03K13/02

    CPC classification number: H03M1/00 ,  H03M2201/02 ,  H03M2201/3115 ,  H03M2201/3131 ,  H03M2201/3136 ,  H03M2201/3168 ,  H03M2201/4135 ,  H03M2201/4225 ,  H03M2201/4233 ,  H03M2201/4262 ,  H03M2201/6121 ,  H03M2201/63 ,  H03M2201/814

    Abstract: A multi-stage resistive ladder network which uses extra stages to trim out resistance discrepencies. All of the stages are interconnected in a series. Nominally, current is divided in half within each stage. Half of the current is gated onto a bus in response to logic control signals, and the other half of the current is passed onto the next succeeding stage. Due to various processing limitations, the resistors comprising each stage vary slightly from their nominal value, which in turn upsets the current division. To compensate for this additional current dividing stages are serially connected to the last stage of the ladder. Current from these additional stages are selectively coupled onto the bus in response to the logic signals in addition to the current which is normally coupled thereto.

    Abstract translation: 一个多级电阻梯形网络，使用额外的级来修剪阻抗差异。 所有的阶段都是相互联系的。 名义上，目前在每个阶段都分成两半。 响应于逻辑控制信号，一半的电流被门控在总线上，而另一半的电流被传递到下一个后续阶段。 由于各种处理限制，包括每个级的电阻器与它们的标称值略有不同，这反过来扰乱了当前的划分。 为了补偿这个额外的电流分级级与梯子的最后阶段串联连接。 来自这些附加级的电流除了通常耦合到其上的电流之外还响应于逻辑信号而选择性地耦合到总线上。

    다중 칩 동적 범위 확장(DRE) 오디오 프로세싱 방법들 및 장치들
    27.
    发明公开
    다중 칩 동적 범위 확장(DRE) 오디오 프로세싱 방법들 및 장치들 审中-实审
    多芯片动态范围扩展（DRE）音频处理方法和装置

    公开(公告)号：KR1020170131640A

    公开(公告)日：2017-11-29

    申请号：KR1020177031055

    申请日：2016-03-16

    Applicant: 씨러스 로직 인코포레이티드

    Inventor： 다스테자비 ,  멜런슨존엘.

    IPC: H04R3/04 ,  H03G7/00 ,  H03G9/00 ,  G10L21/0324 ,  H03M1/12 ,  H03M1/18 ,  H04L1/20 ,  H04L27/26

    CPC classification number: H04R3/04 ,  G10L19/167 ,  G10L21/0324 ,  H03G7/007 ,  H03G9/005 ,  H03M1/00 ,  H03M1/12 ,  H03M1/1225 ,  H03M1/18 ,  H03M2201/4135 ,  H04L1/20 ,  H04L27/2647 ,  H04R2430/01 ,  H04R2430/03

    Abstract: 본개시의실시예들에따라, 둘이상의집적회로들을통하는동적범위확장정보를갖는오디오신호들을프로세싱하기위한다중칩 회로는호스트집적회로및 클라이언트집적회로를포함할수 있다. 호스트집적회로는디지털오디오입력신호를위한동적범위확장이득을결정하고, 동적범위확장이득에따라디지털오디오입력신호를프로세싱하고, 상기프로세싱된디지털오디오입력신호에기초한오디오데이터를송신하도록구성될수 있다. 클라이언트집적회로는호스트집적회로에연결될수 있고오디오데이터를수신하도록구성될수 있고, 상기클라이언트집적회로에는동적범위확장이득이제공되고, 클라이언트집적회로는오디오데이터를동적범위확장이득으로프로세싱하도록구성된다.

    Abstract translation: 根据本公开的实施例，用于通过两个或更多个集成电路处理具有动态范围扩展信息的音频信号的多芯片电路可以包括主机集成电路和客户机集成电路。 主机集成电路可以由动态范围扩展增益用于数字音频输入信号来确定，根据动态范围扩展增益，并处理该数字音频输入信号，并且被配置为发送基于处理后的数字音频输入信号的音频数据 。 客户集成电路可以被配置和被连接到主机集成电路接收所述音频数据，所述客户端的集成电路上设置有动态范围扩展增益，客户集成电路被配置为通过将动态范围扩展增益来处理音频数据 。

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