公开(公告)号：JPH05168146A

公开(公告)日：1993-07-02

申请号：JP11614492

申请日：1992-05-08

Applicant: CONS RIC MICROELETTRONICA

Inventor： PALARA SERGIO ,  SUERI STEFANO

IPC: H02H7/00 ,  F02P3/04 ,  H02H7/12 ,  H03K3/286 ,  H03K17/082

Abstract: PURPOSE: To protect a power transistor by providing a first circuit means for prohibiting the operation of a clamp circuit and a second circuit means for maintaining the clamp circuit in an operating state. CONSTITUTION: First circuit means R1, C1, 8, E1, and T1 prohibit the operation of a clamp circuit 1 for a set time interval, from the time when a power device 3 is switched on until a time when the initial underground of the supply voltage of a power supply device generated due to a resonance load L caused by the ignition of a power device 3 is completed. Second circuit means C2 and TP4 maintain the clamp circuit 1 in an operating state during a second underground of a supply voltage, that is generated due to the resonance load L after the ignition of the power device 3, thus protecting a power transistor.

公开(公告)号：JPH10126171A

公开(公告)日：1998-05-15

申请号：JP35901596

申请日：1996-12-27

Applicant: SGS THOMSON MICROELECTRONICS ,  CONS RIC MICROELETTRONICA

Inventor： ALINI ROBERTO ,  BRUCCOLERI MELCHIORRE ,  COSENTINO GAETANO ,  PISATI VALERIO

IPC: H03F3/30 ,  H03F3/34

Abstract: PROBLEM TO BE SOLVED: To approximate the offset to zero by connecting directly together a drive stage of a complementary push-pull constitution and an output stage, which are cascaded with mutually reverse polarities between the input and output terminals of an amplifier. SOLUTION: A drive stage consists of an input branch part, including a 3rd transistor TR Q3 which is connected in series to a 1st constant current generator G1 between a power terminal and the ground, and a current mirror circuit which includes an output branch part consisting of TR Q4, Q5 and Q6. Then the bases and collectors of the pnp TR Q5 and the npn TR Q6 are connected to an input terminal IN and an output terminal OUT of an amplifier respectively. The emitter of the TR Q5 is connected to a power terminal via a 2nd constant current generator G2, and the emitter of the TR Q6 is grounded via the TR Q4. The output of the drive stage is fetched from the TRs Q5 and Q6 and connected to the bases of the TRs Q1 and Q2 respectively. A bipolar TR can also be converted into an FET.

公开(公告)号：JPH09252115A

公开(公告)日：1997-09-22

申请号：JP28875896

申请日：1996-10-30

Applicant: SGS THOMSON MICROELECTRONICS ,  CONS RIC MICROELETTRONICA

Inventor： MAGRI ANGELO ,  FRISINA FERRUCCIO ,  FERLA GIUSEPPE

IPC: H01L21/336 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To make the contact of source metal layers and main body areas satisfactory even if scaled down to the limit of photolithography and to realize high integration. SOLUTION: Respective basic function unit contain second conductive long main body areas 3 being parallel bars which are formed in a semiconductor material layer and are detached by the distance (d). Main body parts 40 to which first conductive impurities are not given and first conductive source areas 60 are mutually positioned in the respective long main body areas 3. Openings 11 are provided for dielectric layers 9 sealing the conductive layers to be grown to gates along the center parts of the long main body areas 3. The metal layers constituting a source electrode are brought into contact with the source areas 60 and the main body parts 40.

公开(公告)号：JPH09200013A

公开(公告)日：1997-07-31

申请号：JP27821296

申请日：1996-10-21

Applicant: CONS RIC MICROELETTRONICA

Inventor： SARUBUATOOREEBUINSENTSUO KAPII ,  ANTONIO MAGATSUTSU

IPC: H02M3/155 ,  H03K5/00 ,  H03K6/04 ,  H03K7/08

Abstract: PROBLEM TO BE SOLVED: To protect completely the maintenance of synchronization by applying a sawtooth wave signal with a prescribed discharge time by a sufficient time interval enough to compensate a delay to each comparator while being synchronously with the sawtooth wave. SOLUTION: A sawtooth wave signal OSC generated by an oscillator is given to a base of a transistor(TR) Q1 being an input of a circuit. A signal current flowing to high breakdown voltage MOS TRs M4, M9 is equal to a signal current flowing to a TR M5 and TRs Q3, Q4 realizing a voltage follower. In the specific operating state, when a discharge phase of the signal OSC is started, a level of a TR M11 reaches a high level faster than the discharge phase of a signal NEW-OSC. Then a sawtooth wave signal having a shorter discharge time than the discharge time of the signal OSC by a time enough to compensate a delay is generated and given to a comparator PWM. Then the TR M11 reaches a high level faster than the discharge signal of the NEW- OSC to compensate the delay.

公开(公告)号：JPH09167948A

公开(公告)日：1997-06-24

申请号：JP12963996

申请日：1996-05-24

Applicant: SGS THOMSON MICROELECTRONICS ,  CONS RIC MICROELETTRONICA

Inventor： CANTONE GIUSEPPE ,  NOVELLI ALDO

IPC: H03K5/1532 ,  H03K5/1252

Abstract: PROBLEM TO BE SOLVED: To provide a pulse generator provided with one input terminal and with two output terminals from which a pulse is generated respectively depending on an edge of a different type received by the input terminal. SOLUTION: This pulse generator has two separate logic circuit blocks FF1, FF2 of a sequential type and then the production of a pulse at each of two output terminals OR, OS is independently of each other. Thus, the characteristic of each pulse is easily controlled. Furthermore, when the two blocks are interconnected by a proper and simple logic circuit network consisting of G3, G4, it is possible to provide a condition in a simple mode with a degree of freedom between pulses at the two output terminals in the case of producing the pulses.

公开(公告)号：JPH08286921A

公开(公告)日：1996-11-01

申请号：JP7407496

申请日：1996-03-28

Applicant: CONS RIC MICROELETTRONICA

Inventor： BIAJIO JIAKAROONE ,  FURANCHIESUKO PATSUPARAARUDO ,  ENRIKO PEROSU ,  BINCHIENTSUO KATAANIA

IPC: G06F9/44 ,  G06N7/02 ,  G06N7/04

Abstract: PROBLEM TO BE SOLVED: To provide a fuzzy processor having an improved architecture. SOLUTION: The fuzzy processor includes a fuzzy rule processor 1, an internal fuzzy instruction memory 7, an internal intelligent base memory 8, an arithmetic logic device 2, a controller 3 executing a non fuzzy instruction, and an internal memory 5 storing the non fuzzy instruction. The architecture of the improved fuzzy processor loads other intelligent base and other fuzzy rule externally from the processor simultaneously and in a transparent way with respect to the instruction processing. The processor processes both the fuzzy instruction and the non fuzzy instruction and conducts conditional and unconditional jump in a processed fuzzy rule set and swaps conditionally the intelligent base or the rule set to be processed.

公开(公告)号：JPH08272885A

公开(公告)日：1996-10-18

申请号：JP28281995

申请日：1995-10-31

Applicant: CONS RIC MICROELETTRONICA

Inventor： DARIO BURUUNO ,  BIAJIYO JIYAKAROONE ,  NIKORO MANAREESHI

IPC: G06G7/12 ,  G05F3/24 ,  G06N7/04

Abstract: PROBLEM TO BE SOLVED: To obtain an analog device for antecedent count of a fuzzy reference rule by providing an output which acquire an entire truth degree that is related to a fuzzy rule antecedent part to be processed to an one-way element. SOLUTION: A processor 2 contains plural membership function FA analog generators 3. These generators 3 are acquired by a Sasaki generator. Each generator 3 presents an output terminal 4 which is connected to a common circuit node 7. The node 7 is connected to a current generator 9 which sequentially sends out current Imax , a voltage controller 5, a voltage pull-up device 6 and also an one-way element 8. The element 8 constitutes an output 10 of the processor 2.

公开(公告)号：JPH08272470A

公开(公告)日：1996-10-18

申请号：JP6881596

申请日：1996-03-25

Applicant: CONS RIC MICROELETTRONICA ,  SGS THOMSON MICROELECTRONICS

Inventor： ROBERUTO GARIBORUDEI ,  FURANCHIESUKO PURUBUIRENTEI

IPC: G01R19/165 ,  G05F1/46 ,  G05F3/26 ,  G05F3/28 ,  G05F3/30 ,  G11C5/14 ,  H02J1/00

Abstract: PROBLEM TO BE SOLVED: To provide a circuit for generating a reference voltage and simultaneously detecting the drop of a power supply voltage. SOLUTION: In this circuit for generating the reference voltage and detecting the drop of the power supply voltage provided with at least one piece of a threshold value comparator 12 provided with an input terminal IN and an output terminal and a voltage divider 14 connected between a first power supply voltage reference VS and a second voltage reference GND and connected to the input terminal IN of the comparator 12, further, the output terminal OUT of the comparator 12 is connected to the input terminal IN through at least one piece of a feedback network provided with at least one piece of a current generator CG1. The feedback network is further provided with a buffer block 13 provided with the input terminal. connected to the comparator 12 and a first output terminal DO connected to a switch SW and the switch SW is connected between the circuit node X2 of the voltage divider 14 and the second voltage reference GND.

公开(公告)号：JPH0864811A

公开(公告)日：1996-03-08

申请号：JP19326495

申请日：1995-07-28

Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

Inventor： FERLA GIUSEPPE ,  FRISINA FERRUCCIO

IPC: H01L29/78 ,  H01L29/739

Abstract: PROBLEM TO BE SOLVED: To prevent trigger-ons of a parasitic thyristor and to reduce static losses by allowing the sum of the common base current gain of a first bipolar junction type transistor and the current gain of a second bipolar junction type transistor to be 1 or greater. SOLUTION: A source region 11, a channel region 7, and an n-type layer 3 constitute a power MOSFET. The source region 11, a main body region 2, and the n-type layer 3 form the first npn bipolar junction type transistor T1. Furthermore, a substrate 5, the n-type layer 3, and the main body region constitute the second pnp bipolar junction type transistor T2. The sum of base current gains αn and αp of the npn bipolar junction type transistor T1 and pnp bipolar junction type transistor T2 are set so as to be 1 or greater. When the power MOSFET is driven on, both transistors are biased in the forward direction, resulting in αn +αp

公开(公告)号：JPH0846510A

公开(公告)日：1996-02-16

申请号：JP16185695

申请日：1995-06-28

Applicant: SGS THOMSON MICROELECTRONICS ,  CONS RIC MICROELETTRONICA

Inventor： TRAVAGLIA FREDERICO ,  LA ROSA MARIA GRAZIA ,  GIARRIZZO GUIDO

IPC: H03L7/08 ,  G06F9/44 ,  G06N7/02 ,  H03L7/10

Abstract: PURPOSE: To provide a phase locked loop(PLL) circuit equipped with fuzzy control. CONSTITUTION: A PLL circuit 1 is provided with a phase comparator 2 and its output is connected to a low-pass filter 3 for driving a voltage controlled oscillator. The phase comparator 2 generates a signal expressing a phase difference between a signal generated by the oscillator 4 and an input signal. Further, this oscillator 4 is driven by a control signal generated by fuzzy control. The input of fuzzy control is a signal expressing the phase-difference.