公开(公告)号：EP2669935A2

公开(公告)日：2013-12-04

申请号：EP12191602.7

申请日：2012-11-07

Applicant: Unimicron Technology Corp.

Inventor： Tzyy-Jang, Tseng ,  Dyi-Chung, Hu

IPC: H01L21/48 ,  H01L23/498

Abstract: A packaging substrate (100) including following elements is provided. The insulation supporting layer (120) is disposed on a first surface (112) of the multilayered interconnect board (110) and has an opening region (R10). A portion of the first surface (112) is exposed at the opening region (R10). The interposer (130) is disposed on the first surface (112) at the opening region (R10). A third surface (130A) of the interposer (130) faces the first surface (112) of the multilayered interconnect board (110). A stress releasing gap (136) is between an outer-sidewall of the interposer (130) and an inner-sidewall of the opening region (R10). The compliant layer (170) is disposed between the third surface (130A) and the first surface (112). The interposer (130) has through holes (132) and conductive posts (134) disposed in the through holes (132). The conductive posts (134) penetrate the compliant layer (170) and electrically connect with the multilayered interconnect board (110). The redistribution layer (140) is disposed on a fourth surface (130B) of the interposer (130) and is electrically connected with the conductive posts (134).

Abstract translation: 提供包括以下元件的封装基板（100）。 绝缘支撑层（120）设置在多层互连板（110）的第一表面（112）上并具有开口区域（R10）。 第一表面（112）的一部分在开口区域（R10）处露出。 插入器（130）在开口区域（R10）处设置在第一表面（112）上。 内插器（130）的第三表面（130A）面向多层互连板（110）的第一表面（112）。 应力释放间隙（136）位于插入件（130）的外侧壁和开口区域（R10）的内侧壁之间。 柔性层（170）设置在第三表面（130A）和第一表面（112）之间。 插入器（130）具有设置在通孔（132）中的通孔（132）和导电柱（134）。 导电柱（134）穿透顺应层（170）并与多层互连板（110）电连接。 再分配层（140）设置在插入件（130）的第四表面（130B）上并与导电柱（134）电连接。

公开(公告)号：EP2667411A1

公开(公告)日：2013-11-27

申请号：EP12180711.9

申请日：2012-08-16

Applicant: Unimicron Technology Corp.

Inventor： Chen, Tsung-Yuan ,  Cheng, Wei-Ming

IPC: H01L27/146 ,  H01L31/0203

CPC classification number: H01L27/14618 ,  H01L21/56 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/315 ,  H01L24/19 ,  H01L24/20 ,  H01L27/14625 ,  H01L27/14636 ,  H01L27/14689 ,  H01L2224/04105 ,  H01L2924/12042 ,  H01L2924/1815 ,  H01L2924/00

Abstract: A sensing device package structure including a middle dielectric layer (120), a sensing device (130), a front dielectric layer (150), a front patterned conductive layer (170) and at least one front conductive via (180A) is provided. The middle dielectric layer (120) has an anterior surface (120c), a posterior surface (120b) and a middle opening (120a). The sensing device (130) is disposed in the middle opening (120a). The sensing device (130) has a front surface (130a), a back surface (130b), a sensing region (130c), a blocking pattern (132), and at least one electrode (134). The front dielectric layer (150) is disposed on the anterior surface (120c) of the middle dielectric layer (120) and the front surface (130a) of the sensing device (130). The front dielectric layer (150) has a front opening (150a) exposed the sensing region (130c) and the blocking pattern (132). The front patterned conductive layer (170) is disposed on the front dielectric layer (150). The front conductive via (180A) penetrates through the front dielectric layer (150) and connects the front patterned conductive layer (170) and the electrode (134).

Abstract translation: 提供了包括中间介电层（120），感测装置（130），前介电层（150），前图案化导电层（170）和至少一个前导电通孔（180A）的感测装置封装结构。 中间电介质层（120）具有前表面（120c），后表面（120b）和中间开口（120a）。 感测装置（130）设置在中间开口（120a）中。 感测装置（130）具有前表面（130a），后表面（130b），感测区域（130c），阻挡图案（132）和至少一个电极（134）。 前介电层（150）设置在中介电层（120）的前表面（120c）和感测装置（130）的前表面（130a）之间。 前介电层（150）具有暴露感测区域（130c）和阻挡图案（132）的前开口（150a）。 前图案化导电层（170）设置在前介电层（150）上。 前导电通孔（180A）穿过前介电层（150）并连接前图案化导电层（170）和电极（134）。

公开(公告)号：EP2560201A2

公开(公告)日：2013-02-20

申请号：EP11194105.0

申请日：2011-12-16

Applicant: Unimicron Technology Corp.

Inventor： Hu, Dyi-Chung ,  Hu, Yu-Shan

IPC: H01L23/36 ,  H01L23/367 ,  H01L23/538

CPC classification number: H01L23/5389 ,  H01L23/36 ,  H01L23/3677 ,  H01L24/97 ,  H01L2224/45144 ,  H01L2224/4824 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/00015 ,  H01L2924/00

Abstract: A semiconductor packaging structure includes a semiconductor chip, a packaging layer, a dielectric layer, a wiring layer, and a metallic foil. The semiconductor chip has an active surface, an inactive surface opposing the active surface, electrode pads formed on the active surface, and metal bumps formed on the electrode pads. The packaging layer encapsulates the semiconductor chip and exposes the active surface. The dielectric layer is formed on the active surface and a surface of the packaging layer at the same side with the active surface, and has wiring pattern openings for the metal bumps to be exposed therefrom. The wiring layer is formed in the wiring pattern openings. The metallic foil is disposed on the packaging layer adjacent to the inactive surface. Metallic protrusions are formed on the metallic foil, and penetrate the packaging layer to extend to the inactive surface of the semiconductor chip.

Abstract translation: 半导体封装结构包括半导体芯片，封装层，电介质层，布线层和金属箔。 半导体芯片具有活性表面，与活性表面相对的非活性表面，形成在活性表面上的电极焊盘以及形成在电极焊盘上的金属凸块。 包装层封装半导体芯片并暴露活性表面。 电介质层在活性表面和与活性表面相同侧的包装层的表面上形成，并且具有用于金属凸块暴露的布线图案孔。 布线层形成在布线图形开口中。 金属箔设置在与非活性表面相邻的包装层上。 在金属箔上形成金属突起，穿透包装层延伸到半导体芯片的非活性表面。

公开(公告)号：EP2555240A1

公开(公告)日：2013-02-06

申请号：EP12179424.2

申请日：2012-08-06

Applicant: Unimicron Technology Corp. ,  Industrial Technology Research Institute

Inventor： Hu, Dyi-Chung ,  Lau, John Hon-Shing

IPC: H01L25/065 ,  H01L23/14 ,  H01L23/498

Abstract: A packaging substrate includes a carrier and an interposer. The carrier has opposite top and bottom surfaces. A recess is disposed in the top surface and a plurality of first conductive terminals are disposed on the bottom of the recess. Further, a plurality of second conductive terminals are disposed on the bottom surface of the carrier. The interposer is disposed in the recess and has opposite first and second surfaces and a plurality of conductive through vias penetrating the first and second surfaces. A first conductive pad is disposed on an end of each of the conductive through vias exposed from the first surface, and a second conductive pad is disposed on the other end of the conductive through via exposed from the second surface and electrically connected to a corresponding one of the first conductive terminals. Compared with the prior art, the invention improves the product reliability.

Abstract translation: 甲封装基板包括载体和在中介层上。 该载体具有相对的顶部和底部表面。 的凹部在其顶表面设置，并且第一导电端子的多元化是在凹部的底部处。 此外，第二导电端子的多元被设置在载体的下表面上。 该内插器是在所述凹部设置，并且具有相对的第一和第二表面和通孔穿透第一和第二表面的导电复数。 第一导电垫被设置在每个导电的端部通过从所述第一表面暴露的通孔设置在和第二导电板经由通孔从所述第二表面暴露的并且电连接到相应的一个设置在导电的另一端 的第一导电端子。 与现有技术相比，本发明提高了产品的可靠性。

公开(公告)号：EP2020835B1

公开(公告)日：2012-07-25

申请号：EP08009013.7

申请日：2008-05-15

Applicant: Unimicron Technology Corp.

Inventor： Hsu, Shih-Ping

IPC: H05K3/34 ,  H05K3/24

CPC classification number: H05K3/3473 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05567 ,  H01L2224/05644 ,  H01L2224/05671 ,  H01L2224/13109 ,  H05K3/243 ,  H05K3/3452 ,  H05K2201/0367 ,  H05K2201/0989 ,  H05K2203/043 ,  H05K2203/0542 ,  H01L2924/00014

公开(公告)号：EP2120519B1

公开(公告)日：2011-12-28

申请号：EP09250489.3

申请日：2009-02-24

Applicant: Unimicron Technology Corp.

Inventor： Chen, Tsung-Yuan ,  Chiang, Shu-Sheng ,  Cheng, David C. H.

IPC: H05K3/02 ,  H05K1/00 ,  H05K1/11 ,  H05K3/10 ,  H05K3/00

CPC classification number: H05K3/465 ,  H05K1/0265 ,  H05K3/0032 ,  H05K3/0038 ,  H05K3/107 ,  H05K3/426 ,  H05K3/428 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/09536 ,  H05K2201/09736 ,  Y10T29/49147

公开(公告)号：US12250776B2

公开(公告)日：2025-03-11

申请号：US18317756

申请日：2023-05-15

Applicant: UNIMICRON TECHNOLOGY CORP.

Inventor： Jeng-Ting Li ,  Chi-Hai Kuo ,  Cheng-Ta Ko ,  Pu-Ju Lin

IPC: H05K3/00 ,  C03C15/00 ,  C03C23/00 ,  H05K1/03

Abstract: A substrate structure and a cutting method thereof are provided. The cutting method includes the following steps. A first substrate structure is provided, wherein the first substrate structure includes a glass substrate and a redistribution layer disposed on the glass substrate. A laser process is performed on the glass substrate to form a modified region on the glass substrate. A wet etching process is performed on the modified region of the glass substrate to remove the modified region and form a plurality of second substrate structures.

公开(公告)号：US12185479B2

公开(公告)日：2024-12-31

申请号：US17945106

申请日：2022-09-15

Applicant: Unimicron Technology Corp.

Inventor： Cheng-Ta Ko ,  Pu-Ju Lin ,  Shih-Chieh Chen ,  Chi-Hai Kuo ,  Jeng-Ting Li

IPC: H05K1/03 ,  H05K1/11 ,  H05K3/06 ,  H05K3/46

Abstract: A flexible circuit board and a manufacturing method thereof are provided. The flexible circuit board includes a circuit structure, a first cover layer, and a second cover layer. The circuit structure has a top surface and a bottom surface opposite to the top surface. The circuit structure includes multiple circuit layers and multiple insulating layers stacked alternately. A material of the insulating layers is a photosensitive dielectric material and a Young's modulus of the insulating layers is between 0.36 GPa and 8 GPa. The first cover layer is disposed on the top surface of the circuit structure. The second cover layer is disposed on the bottom surface of the circuit structure.

公开(公告)号：US12184005B2

公开(公告)日：2024-12-31

申请号：US17661282

申请日：2022-04-28

Applicant: Unimicron Technology Corp.

Inventor： Ching-Ho Hsieh ,  Ming-Hsing Wu ,  Keui-Sheng Wu

IPC: H01R13/17 ,  H01R12/70

Abstract: A connector includes a substrate, a coverlay and a spring contact. The substrate has a first surface, a second surface opposite to the first surface and a conductive through hole extending between the first and second surfaces. The coverlay is disposed on the first surface and includes a first opening. The spring contact includes an anchor member, a rising member and a pin. The anchor member is disposed between the substrate and the coverlay. The rising member extends from the anchor member and through the first opening in a direction away from the substrate. A first portion of the rising member is in the first opening, and a second portion of the rising member is out of the first opening. The pin extends from the anchor member to an inside of the conductive through hole, and is electrically connected to the conductive through hole.

公开(公告)号：US20240389232A1

公开(公告)日：2024-11-21

申请号：US18220548

申请日：2023-07-11

Applicant: UNIMICRON TECHNOLOGY CORP.

Inventor： Chun Hung KUO ,  Kuo-Ching CHEN ,  Yu-Cheng HUANG ,  Yu-Hua CHEN

IPC: H05K1/14 ,  H05K1/16 ,  H05K3/36

Abstract: A circuit board structure and a manufacturing method thereof. Circuit board structure includes first circuit board, second circuit board, conductive coil, magnetic body and molding compound. First circuit board has first side surface and first cavity located on first side surface. Second circuit board has second side surface facing first side surface and being spaced apart from first side surface. Conductive coil is in a spiral shape and includes first coil pattern and second coil pattern. First coil pattern is disposed in first circuit board. Second coil pattern is disposed in second circuit board. First coil pattern is electrically connected to second coil pattern. Magnetic body is filled in first cavity of first circuit board. Conductive coil surrounds at least a part of magnetic body. Molding compound is filled in a gap between first side surface and second side surface.