公开(公告)号：KR100446517B1

公开(公告)日：2004-09-04

申请号：KR1020020005393

申请日：2002-01-30

Applicant: 삼성전자주식회사

Inventor： 구준모

IPC: H01L21/205

Abstract: PURPOSE: A flame hydrolysis deposition apparatus for silicon wafer fabrication is provided to form uniformly a silica layer on the surface of a silicon wafer by using two or more torches for performing an oxidation process and a hydrolysis process. CONSTITUTION: A flame hydrolysis deposition apparatus for fabricating a silicon wafer includes a turntable(23a), a plurality of torches(25a,25b), and a plurality of absorption and exhaust units(27a,27b). The turntable is used for loading and rotating a plurality of silicon wafers. The torches are used for generating silica particles by using an oxidation process and a hydrolysis process for flame material gases and chemical reaction gases. The absorption and exhaust units are used for absorbing or exhausting the silica particles which are not deposited on the silicon wafer. The torches are arranged in an interval of the same angle.

Abstract translation: 目的：提供一种用于硅晶片制造的火焰水解沉积设备，以通过使用两个或更多个炬进行氧化处理和水解处理，在硅晶片的表面上均匀地形成二氧化硅层。 构成：用于制造硅晶片的火焰水解沉积设备包括转盘（23a），多个喷灯（25a，25b）以及多个吸收和排气单元（27a，27b）。 转盘用于装载和旋转多个硅晶片。 炬用于通过使用火焰材料气体和化学反应气体的氧化过程和水解过程来产生二氧化硅颗粒。 吸收和排气单元用于吸收或排出未沉积在硅晶片上的二氧化硅颗粒。 火炬以相同角度的间隔排列。

公开(公告)号：KR102034482B1

公开(公告)日：2019-10-21

申请号：KR1020130022858

申请日：2013-03-04

Applicant: 삼성전자주식회사

Inventor： 구준모 ,  김남길 ,  문창록 ,  박병준 ,  신종철

IPC: H04N5/361 ,  H04N5/374

公开(公告)号：KR101648200B1

公开(公告)日：2016-08-12

申请号：KR1020090100581

申请日：2009-10-22

Applicant: 삼성전자주식회사

Inventor： 최상준 ,  구준모 ,  문창록 ,  박윤동 ,  배대록 ,  안정착 ,  홍성권 ,  김석필 ,  오훈상

IPC: H01L27/146

CPC classification number: H01L27/14641 ,  H01L21/76898 ,  H01L23/481 ,  H01L27/14612 ,  H01L27/14632 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14687 ,  H01L2224/9212 ,  H01L2224/80896 ,  H01L2224/8203 ,  H01L2224/821 ,  H01L2224/80001 ,  H01L2224/82

Abstract: 이미지센서및 그제조방법에서, 이미지센서는리셋트랜지스터, 변환트랜지스터및 선택트랜지스터가형성된제1 기판이구비된다. 상기제1 기판상에, 상기리셋트랜지스터, 변환트랜지스터및 선택트랜지스터를덮는제1 실리콘산화막이구비된다. 포토다이오드, 전송트랜지스터및 플로팅확산영역이형성된제2 기판이구비된다. 상기포토다이오드, 전송트랜지스터및 플로팅확산영역을덮는형상을갖고, 표면부위가상기제1 실리콘산화막의상부면과본딩된제2 실리콘산화막이구비된다. 상기제2 기판및 제2 실리콘산화막을관통하고, 계속하여상기제1 실리콘산화막의일부를관통하는콘택플러그를포함한다. 상기이미지센서는고집적화되고고성능을갖는다.

公开(公告)号：KR1020100013886A

公开(公告)日：2010-02-10

申请号：KR1020080075619

申请日：2008-08-01

Applicant: 삼성전자주식회사

Inventor： 윤태응 ,  김원주 ,  구준모 ,  김석필 ,  이태희

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: G11C8/14 ,  G11C5/02 ,  G11C5/025 ,  H01L27/2436 ,  H01L27/2463

Abstract: PURPOSE: A non-volatile memory device and a method of operating the same are provided to implement random access to memory cells by appropriately selecting a bit line and a word line. CONSTITUTION: A plurality of variable resistance members(R) are capable of being stacked in one layer and storing data. At least one bit line for selecting layers is combined with a first end of a plurality of variable resistance member. A plurality of bit line(BL1,BL2,BL3) are combined with a second end(a2) of a plurality of variable resistance member. A plurality of select transistors(Ts) are combined between a plurality of bit lines and plurality of variable resistance member. A plurality of word line(WL1,WL2,WL3) are combined with a plurality of select transistors in order to control the on-off of a plurality of select transistors.

Abstract translation: 目的：提供非易失性存储器件及其操作方法，通过适当地选择位线和字线来实现对存储器单元的随机存取。 构成：多个可变电阻构件（R）能够堆叠在一层中并存储数据。 用于选择层的至少一个位线与多个可变电阻构件的第一端组合。 多个位线（BL1，BL2，BL3）与多个可变电阻部件的第二端（a2）组合。 多个选择晶体管（Ts）组合在多个位线和多个可变电阻部件之间。 多个字线（WL1，WL2，WL3）与多个选择晶体管组合，以便控制多个选择晶体管的导通。

公开(公告)号：KR1020100007254A

公开(公告)日：2010-01-22

申请号：KR1020080067812

申请日：2008-07-11

Applicant: 삼성전자주식회사

Inventor： 김석필 ,  박윤동 ,  구준모 ,  윤태응

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L27/11551 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/76224 ,  H01L27/11556

Abstract: PURPOSE: A non-volatile memory device and method of fabricating the same are provided to improve the degree of integration. CONSTITUTION: The stack structure of the second control gate electrode(120b) and the first control gate electrode(120a) is offered with a plurality of lines. The stack structure of first control gate electrodes and stack structure of second control gate electrodes are by turns arranged. First control gate electrodes and second control gate electrodes are arranged two-dimensionally in on the plane. A plurality of interlayer dielectric layer(110) is offered between interval and the second semiconductor layer(160b) of the semiconductor layer(160a).

Abstract translation: 目的：提供非易失性存储器件及其制造方法以提高积分度。 构成：第二控制栅电极（120b）和第一控制栅电极（120a）的堆叠结构具有多条线。 第一控制栅极的堆叠结构和第二控制栅电极的堆叠结构依次排列。 第一控制栅电极和第二控制栅极电极在二维平面上排列。 在半导体层（160a）的间隔和第二半导体层（160b）之间提供多个层间电介质层（110）。

公开(公告)号：KR1020100007229A

公开(公告)日：2010-01-22

申请号：KR1020080067766

申请日：2008-07-11

Applicant: 삼성전자주식회사

Inventor： 김석필 ,  박윤동 ,  구준모 ,  윤태응

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L27/11556 ,  H01L27/11521 ,  H01L27/11551 ,  H01L27/11578 ,  H01L21/28273 ,  H01L21/28282

Abstract: PURPOSE: A non-volatile memory device and method of fabricating the same are provided to improve the degree of integration. CONSTITUTION: A plurality of semiconductor layers(120a) is laminated in a plurality of layers. A plurality of second semiconductor layers(120b) is laminated in a plurality of layers. A plurality of interlayer dielectric layer(110) is offered between interval and second semiconductor layers of semiconductor layers. The first control gate electrode(160a) is extended through semiconductor layers. Each first blocking insulating layer(150a) is extended through semiconductor layers.

Abstract translation: 目的：提供非易失性存储器件及其制造方法以提高积分度。 构成：将多个半导体层（120a）层叠成多层。 多个第二半导体层（120b）层叠成多层。 在半导体层的间隔和第二半导体层之间提供多个层间介质层（110）。 第一控制栅电极（160a）延伸穿过半导体层。 每个第一阻挡绝缘层（150a）延伸穿过半导体层。

公开(公告)号：KR1020090035203A

公开(公告)日：2009-04-09

申请号：KR1020070100344

申请日：2007-10-05

Applicant: 삼성전자주식회사

Inventor： 이태희 ,  김원주 ,  박윤동 ,  구준모 ,  김석필 ,  윤태응

IPC: G11C16/00

CPC classification number: G11C16/0483 ,  H01L27/11521 ,  H01L27/11568

Abstract: A non-volatile memory device and an operation method thereof are provided to suppress the damage of outermost memory cell transistors by performing the programming and read out operation without using the channel boosting. A non-volatile memory device comprises one or more main strings(MS1,MS2) and a charge supply line(CSL). The main string comprises the first sub string(TM1_1~TMn_1) and the second sub string(TM1_2~TMn_2). Each substring comprises a plurality of memory cell transistors. The charge sourcing line supplies or blocks the electric charge to the first and second sub strings of the main string. The main string comprises the first and second ground-selection transistors(TGS1,TGS3,TGS2,TGS4) and the first and second sub string selection transistors(TSI1,TSI3,TSI2,TSI4). The first and second ground-selection transistors are connected to the first and second sub strings. The first and second sub string selection transistors are connected to the first and second ground-selection transistors.

Abstract translation: 提供一种非易失性存储器件及其操作方法，以通过在不使用通道升压的情况下执行编程和读出操作来抑制最外存储单元晶体管的损坏。 非易失性存储器件包括一个或多个主串（MS1，MS2）和充电电源线（CSL）。 主串包括第一子串（TM1_1〜TMn_1）和第二子串（TM1_2〜TMn_2）。 每个子串包括多个存储单元晶体管。 电荷源线向主串的第一和第二子串提供或阻断电荷。 主串包括第一和第二接地选择晶体管（TGS1，TGS3，TGS2，TGS4）和第一和第二子串选择晶体管（TSI1，TSI3，TSI2，TSI4）。 第一和第二接地选择晶体管连接到第一和第二子串。 第一和第二子串选择晶体管连接到第一和第二接地选择晶体管。

公开(公告)号：KR1020090017041A

公开(公告)日：2009-02-18

申请号：KR1020070081460

申请日：2007-08-13

Applicant: 삼성전자주식회사

Inventor： 구준모 ,  김석필 ,  진영구 ,  김원주 ,  유인경 ,  박윤동

IPC: H01L27/115

CPC classification number: H01L29/66825 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7881 ,  H01L21/28141

Abstract: A nonvolatile memory device and a manufacturing method thereof are provided to enhance degree of integration by shortening width and separation distance of pins, and to reduce a leakage current and an off current by preventing single channel effect. A semiconductor substrate(110) includes a body(102) and a pair of pins(105a, 105b). A pair of pins is protruded from the body. An insulating layer(157) is filled between a pair of pins. A pair of floating gate electrodes(130a, 130b) is formed on a side of a pair of pins. The floating gate electrodes are higher than a pair of pins. A gate electrode(140) is positioned on a pair of floating gate electrodes.

Abstract translation: 提供非易失性存储器件及其制造方法，以通过缩短引脚的宽度和间隔距离来提高集成度，并且通过防止单通道效应来减少漏电流和截止电流。 半导体衬底（110）包括主体（102）和一对销（105a，105b）。 一对针脚从身体突出。 绝缘层（157）填充在一对销之间。 一对浮栅电极（130a，130b）形成在一对引脚的一侧。 浮栅电极高于一对引脚。 栅电极（140）位于一对浮栅上。

公开(公告)号：KR1020080060657A

公开(公告)日：2008-07-02

申请号：KR1020060135005

申请日：2006-12-27

Applicant: 삼성전자주식회사

Inventor： 송승환 ,  김석필 ,  박윤동 ,  김원주 ,  구준모 ,  조경래 ,  현재웅 ,  변성재

IPC: H01L21/336

CPC classification number: H01L29/785 ,  H01L21/76897 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7851 ,  H01L29/7881 ,  H01L29/792 ,  H01L2029/7858

Abstract: A semiconductor device and a manufacturing method thereof are provided to prevent penetration of conductive materials into a void by blocking the expansion of a void between fins using a semiconductor pillar. A semiconductor substrate comprises a pair of fins(105a,105b) which are used as an active region. A semiconductor pillar(105d) is inserted between the pins in order to connect the pair of pins. A contact plug is formed on the semiconductor pillar so as to be connected to the upper plane of the pair of fins. Wherein, the fin and the semiconductor pillar are formed of the same semiconductor material.

Abstract translation: 提供半导体器件及其制造方法，以防止导电材料通过使用半导体柱阻挡在翅片之间的空隙的膨胀而渗透到空隙中。 半导体衬底包括用作有源区的一对散热片（105a，105b）。 半导体柱（105d）插入在引脚之间以便连接该对引脚。 接触插塞形成在半导体柱上，以便与一对鳍片的上平面连接。 其中，鳍和半导体柱由相同的半导体材料形成。

公开(公告)号：KR1020080048314A

公开(公告)日：2008-06-02

申请号：KR1020060118559

申请日：2006-11-28

Applicant: 삼성전자주식회사

Inventor： 김원주 ,  김석필 ,  박윤동 ,  구준모

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: G11C11/5678 ,  G11C13/0004 ,  H01L27/24 ,  H01L27/2463

Abstract: A non-volatile memory device and a manufacturing method thereof are provided to reduce a manufacturing cost by forming unit cells of a multilayered structure. One or more first semiconductor layers(110) of a first conductive type is stacked apart from each other on a part of a substrate(105). A plurality of resistance change storage layers(155) are formed on the first semiconductor layers in order to cover sidewalls of the semiconductor layers. A plurality of second semiconductor layers(150) of a second conductive type are inserted between the first semiconductor layers and the first resistance change storage layers. The second conductive type is opposite to the first conductive type. A plurality of bit lines connected to the first resistance change storage layers.

Abstract translation: 提供了一种非易失性存储器件及其制造方法，以通过形成多层结构的单元来降低制造成本。 第一导电类型的一个或多个第一半导体层（110）在衬底（105）的一部分上彼此分离堆叠。 为了覆盖半导体层的侧壁，在第一半导体层上形成有多个电阻变化存储层（155）。 多个第二导电类型的第二半导体层（150）插入在第一半导体层和第一电阻变化存储层之间。 第二导电类型与第一导电类型相反。 连接到第一电阻变化存储层的多个位线。