公开(公告)号：KR1020090062373A

公开(公告)日：2009-06-17

申请号：KR1020070129581

申请日：2007-12-13

Applicant: 한국전자통신연구원

Inventor： 양종헌 ,  백인복 ,  안창근 ,  박찬우 ,  김안순 ,  유한영 ,  아칠성 ,  김태엽 ,  전명심 ,  장문규

IPC: H01L21/336 ,  H01L29/78

CPC classification number: G01N27/4145 ,  H01L29/66818 ,  H01L29/7853

Abstract: A high sensitive sensor and a manufacturing method thereof are provided to obtain a high signal by controlling depletion and accumulation of a channel by combining a target material and a sensing material in both sides. An SOI(Silicon On Insulator) substrate is formed in an upper part of a semiconductor substrate. A mask pattern is formed by performing a lithography process in the upper part of the SOI substrate. The structure of a pin shape is formed by etching a silicon layer in the upper part of the SOI substrate. The sensor structure with a pin shaped structure is formed on the semiconductor substrate. A metal electrode is deposited by implanting the ion for electrical ohmic contact to the sensor structure. A sensing material combined in a target material is fixed in both sidewalls of the pin shaped structure. The path for penetrating the target material through the pin-shaped structure is formed on the sensor structure.

Abstract translation: 提供了一种高灵敏度传感器及其制造方法，以通过在两侧组合目标材料和感测材料来控制通道的耗尽和累积来获得高信号。 在半导体衬底的上部形成SOI（绝缘体上硅）衬底。 通过在SOI衬底的上部进行光刻工艺来形成掩模图案。 针状结构通过在SOI衬底的上部蚀刻硅层而形成。 具有针状结构的传感器结构形成在半导体衬底上。 通过将用于电欧姆接触的离子注入传感器结构来沉积金属电极。 组合在目标材料中的感测材料固定在销形结构的两个侧壁中。 在传感器结构上形成穿过针状结构穿透目标材料的路径。

公开(公告)号：KR1020090058883A

公开(公告)日：2009-06-10

申请号：KR1020070125679

申请日：2007-12-05

Applicant: 한국전자통신연구원

Inventor： 박찬우 ,  안창근 ,  양종헌 ,  백인복 ,  아칠성 ,  유한영 ,  김안순 ,  김태엽 ,  장문규 ,  전명심

IPC: H01L29/00 ,  G01N27/00 ,  G01N33/48 ,  B82Y15/00

CPC classification number: H01L29/0665 ,  B82Y10/00 ,  B82Y15/00 ,  H01L29/0673 ,  H01L29/78696

Abstract: A semiconductor nano wire sensor and a manufacturing method thereof are provided to implement a silicon nano wire channel of a line width with several nano meters by using a photolithographic process. A first conductive single crystal silicon line pattern is formed in the uppermost layer of an SOI(Silicon On Insulator) substrate. A second conductive channel(216b) is formed in both ends of the line width direction of the first conductive single crystal silicon line pattern. The second conductive pad is formed in both sides of the longitudinal direction of the first conductive single crystal silicon line pattern. A first electrode(242) for applying a reverse bias voltage is formed in an undoped region of the first conductive single crystal silicon line pattern. A second electrode(232) for applying the bias voltage to both sides of the second conductive channel is formed on the second conductive pad.

Abstract translation: 提供半导体纳米线传感器及其制造方法，通过使用光刻工艺来实现具有数纳米的线宽的硅纳米线通道。 在SOI（绝缘体上硅）衬底的最上层形成第一导电单晶硅线图形。 第二导电沟道（216b）形成在第一导电单晶硅线图案的线宽方向的两端。 第二导电焊盘形成在第一导电单晶硅线图案的纵向方向的两侧。 在第一导电单晶硅线图案的未掺杂区域中形成用于施加反向偏置电压的第一电极（242）。 在第二导电焊盘上形成用于将偏置电压施加到第二导电沟道两侧的第二电极（232）。

公开(公告)号：KR100864871B1

公开(公告)日：2008-10-22

申请号：KR1020070051780

申请日：2007-05-29

Applicant: 한국전자통신연구원

Inventor： 최철종 ,  장문규 ,  김약연 ,  전명심 ,  김태엽

IPC: H01L29/78 ,  H01L29/772

CPC classification number: H01L21/28229 ,  H01L21/28079 ,  H01L29/495 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/7833

Abstract: A method for manufacturing a semiconductor device is provided to obtain a high dielectric gate oxide by using an interface reaction between an oxide layer and a metal layer. An oxide layer(20) is formed on a silicon substrate(10). A metal layer(30) is deposited on the oxide layer. A metal silicate layer(40) is formed between the oxide layer and the metal layer by using an interface reaction between the oxide layer and the metal layer. A metal gate is formed by etching the metal silicate layer and the metal layer. An LDD(Lightly Doped Drain) region and source/drain electrodes are formed on the silicon substrate. The interface reaction is induced by performing a thermal process after the metal layer is deposited on the oxide layer or by using kinetic energy caused by a deposition process of the metal layer on the oxide layer.

Abstract translation: 提供一种制造半导体器件的方法，以通过使用氧化物层和金属层之间的界面反应来获得高电介质栅极氧化物。 在硅衬底（10）上形成氧化物层（20）。 金属层（30）沉积在氧化物层上。 通过使用氧化物层和金属层之间的界面反应，在氧化物层和金属层之间形成金属硅酸盐层（40）。 通过蚀刻金属硅酸盐层和金属层形成金属栅极。 在硅衬底上形成LDD（轻掺杂漏极）区域和源/漏电极。 在金属层沉积在氧化物层上之后或通过使用由氧化物层上的金属层的沉积工艺引起的动能，通过进行热处理来诱导界面反应。

公开(公告)号：KR1020080051030A

公开(公告)日：2008-06-10

申请号：KR1020070100558

申请日：2007-10-05

Applicant: 한국전자통신연구원

Inventor： 전명심 ,  장문규 ,  김약연 ,  최철종 ,  김태엽 ,  이성재

IPC: H01L27/098 ,  H01L27/095 ,  B82Y40/00

CPC classification number: H01L29/0673

Abstract: A schottky barrier nano-wire field effect transistor and a manufacturing method thereof are provided to secure thermal stability by forming a source/drain electrode using metal silicide when the source/drain electrode is jointed to a nano-wire. A channel(140) made of nano-wire is formed on a substrate(100). A source/drain electrode(150) made of metal silicide is formed on the upper surface of a substrate, and is electrically connected to both ends of the channel. A gate electrode(170) is formed to enclose the channel, and a gate insulating layer(160) is formed between the channel and the gate electrode. The nano-wire is made of any one selected from a group consisting of ZnO, V2O5, GaN and AlN.

Abstract translation: 提供肖特基势垒纳米线场效应晶体管及其制造方法，用于通过在源/漏电极连接到纳米线时通过使用金属硅化物形成源极/漏极来确保热稳定性。 在衬底（100）上形成由纳米线制成的通道（140）。 由金属硅化物制成的源极/漏极（150）形成在衬底的上表面上，并且电连接到沟道的两端。 形成栅电极（170）以包围沟道，并且在沟道和栅电极之间形成栅极绝缘层（160）。 纳米线由选自ZnO，V2O5，GaN和AlN的任何一种制成。

公开(公告)号：KR100789922B1

公开(公告)日：2008-01-02

申请号：KR1020060118985

申请日：2006-11-29

Applicant: 한국전자통신연구원

Inventor： 최철종 ,  장문규 ,  김약연 ,  김태엽 ,  전명심 ,  이성재

IPC: H01L21/24 ,  H01L29/78

CPC classification number: H01L21/28088 ,  H01L29/4966 ,  H01L29/78 ,  H01L29/0847 ,  H01L29/665

Abstract: A method for manufacturing a semiconductor device and a semiconductor device manufactured using the same are provided to form a semiconductor device to which a metal silicide is adopted without a space structure by forming a gate electrode with a conductive compound. A gate dielectric is formed on a substrate(10). A conductive compound, which is not reacted with a metal layer to be formed through a subsequent process, is formed on the gate dielectric. The conductive compound and the gate dielectric are etched to form a gate electrode(12A). The metal layer is formed on a top of the substrate including the gate electrode. The metal and silicon contained in the substrate are reacted to form a source and drain region(14) comprised of a metal silicide layer on the substrate exposed at both sides of the gate electrode. After forming the metal silicide layer, the remaining metal layer which is not reacted with the silicon is removed.

Abstract translation: 提供一种制造半导体器件的方法和使用其制造的半导体器件，以形成通过形成具有导电化合物的栅电极而不具有空间结构的金属硅化物的半导体器件。 在基板（10）上形成栅极电介质。 在栅极电介质上形成导电化合物，其不与通过后续工艺形成的金属层反应。 蚀刻导电化合物和栅极电介质以形成栅电极（12A）。 金属层形成在包括栅电极的基板的顶部上。 包含在基板中的金属和硅被反应以形成由栅极电极的两侧露出的基板上的金属硅化物层构成的源区和漏区（14）。 在形成金属硅化物层之后，除去未与硅反应的剩余金属层。

公开(公告)号：KR1020070059900A

公开(公告)日：2007-06-12

申请号：KR1020060074492

申请日：2006-08-08

Applicant: 한국전자통신연구원

Inventor： 전명심 ,  장문규 ,  김약연 ,  최철종 ,  박병철 ,  이성재

IPC: H01L21/335 ,  H01L29/872

Abstract: A schottky barrier tunnel transistor is provided to form a stable high-performance N-type schottky barrier tunnel transistor with a low schottky barrier with respect to electrons by forming a schottky junction on the (111) surface of a silicon by an anisotropic etch process. An insulation layer(20) is deposited on a substrate(10). A source/drain(30a,30b) is formed on the insulation layer. A channel(90) is formed between the source and the drain. A gate insulation layer(40) and a gate electrode(60) are sequentially formed on the channel. A sidewall insulation layer(50) is formed on both sidewalls of the gate insulation layer and the gate electrode. The interface of one of the source or drain and the channel has a (111) surface of silicon, and at least a part of the source/drain including the silicon (111) surface is silicidized by a predetermined metal material to be a schottky junction. The channel can be higher than the source/drain so that the interface has a slope.

Abstract translation: 提供肖特基势垒隧道晶体管，以通过各向异性蚀刻工艺在硅的（111）表面上形成肖特基结，形成相对于电子具有低肖特基势垒的稳定的高性能N型肖特基势垒隧道晶体管。 绝缘层（20）沉积在衬底（10）上。 源极/漏极（30a，30b）形成在绝缘层上。 在源极和漏极之间形成沟道（90）。 栅极绝缘层（40）和栅电极（60）依次形成在沟道上。 在栅极绝缘层和栅电极的两个侧壁上形成侧壁绝缘层（50）。 源极或漏极和沟道之一的界面具有硅的（111）表面，并且包括硅（111）表面的源极/漏极的至少一部分被预定的金属材料硅化为肖特基结 。 通道可以高于源极/漏极，以使界面具有斜率。

公开(公告)号：KR100699462B1

公开(公告)日：2007-03-28

申请号：KR1020050119010

申请日：2005-12-07

Applicant: 한국전자통신연구원

Inventor： 장문규 ,  이성재 ,  김약연 ,  최철종 ,  전명심

IPC: H01L29/812

CPC classification number: H01L29/458 ,  H01L29/517 ,  H01L29/66643

Abstract: A schottky barrier tunnel transistor and a method for manufacturing the same are provided to form silicide for manufacturing a device having a schottky barrier by performing an ion implantation process and a thermal process. A substrate(300) is prepared. An active silicon layer is formed on the substrate. A gate insulating layer(315) is formed on one region of the silicon layer. A gate electrode(320) is formed on the gate insulating layer. Ions are implanted into a source/drain region(330) of the silicon layer on which the gate insulating layer is not formed. A thermal process for the silicon layer containing the implanted ions is performed. A sidewall spacer is formed on sidewalls of the gate insulating layer and the gate electrode.

Abstract translation: 提供肖特基势垒隧道晶体管及其制造方法，以通过进行离子注入工艺和热处理来形成用于制造具有肖特基势垒的器件的硅化物。 制备基板（300）。 在衬底上形成有源硅层。 在硅层的一个区域上形成栅极绝缘层（315）。 栅电极（320）形成在栅极绝缘层上。 将离子注入到其中未形成栅极绝缘层的硅层的源极/漏极区域（330）中。 进行含有注入离子的硅层的热处理。 在栅极绝缘层和栅电极的侧壁上形成侧壁间隔物。