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    Cache miss thread balancing
    31.
    发明专利
    Cache miss thread balancing 未知

    公开(公告)号：GB2574171B

    公开(公告)日：2020-04-22

    申请号：GB201914312

    申请日：2018-02-27

    Applicant: IBM

    Inventor： GREGORY WILLIAM ALEXANDER ,  SOMIN SONG ,  BRIAN DAVID BARRICK ,  ANTHONY SAPORITO ,  CHRISTIAN JACOBI ,  AARON TSAI ,  THOMAS WINTERS FOX

    IPC: G06F9/38 ,  G06F12/0811

    Abstract: A simultaneous multithread (SMT) processor having a shared dispatch pipeline includes a first circuit that detects a cache miss thread. A second circuit determines a first cache hierarchy level at which the detected cache miss occurred. A third circuit determines a Next To Complete (NTC) group in the thread and a plurality of additional groups (X) in the thread. The additional groups (X) are dynamically configured based on the detected cache miss. A fourth circuit determines whether any groups in the thread are younger than the determined NTC group and the plurality of additional groups (X), and flushes all the determined younger groups from the cache miss thread.

    Reducing cache transfer overhead in a system
    32.
    发明专利
    Reducing cache transfer overhead in a system 未知

    公开(公告)号：GB2577845A

    公开(公告)日：2020-04-08

    申请号：GB202000470

    申请日：2018-06-14

    Applicant: IBM

    Inventor： CHRISTIAN ZOELLIN ,  CHRISTIAN JACOBI ,  CHUNG-LUNG K SHUM ,  MARTIN RECKTENWALD ,  ANTHONY SAPORITO ,  AARON TSAI

    IPC: G06F12/0815

    Abstract: A method and a system detects a cache line as a potential or confirmed hot cache line based on receiving an intervention of a processor associated with a fetch of the cache line. The method and system include suppressing an action of operations associated with the hot cache line. A related method and system detect an intervention and, in response, communicates an intervention notification to another processor. An alternative method and system detect a hot data object associated with an intervention event of an application. The method and system can suppress actions of operations associated with the hot data object. An alternative method and system can detect and communicate an intervention associated with a data object.

    Generating and verifying hardware instruction traces including memory data contents
    33.
    发明专利
    Generating and verifying hardware instruction traces including memory data contents 未知

    公开(公告)号：GB2576288A

    公开(公告)日：2020-02-12

    申请号：GB201917044

    申请日：2018-05-21

    Applicant: IBM

    Inventor： JANG-SOO LEE ,  CHRISTIAN JACOBI ,  CHRISTIAN ZOELLIN ,  DAVID LEE ,  JANE BARTIK ,  ANTHONY SAPORITO

    IPC: G06F9/38

    Abstract: Embodiments of the present invention are directed to a computer-implemented method for generating and verifying hardware instruction traces including memory data contents. The method includes initiating an in-memory trace (IMT) data capture for a processor, the IMT data being an instruction trace collected while instructions flow through an execution pipeline of the processor. The method further includes capturing contents of architected registers of the processor by: storing the contents of the architected registers to a predetermined memory location, and causing a load-store unit (LSU) to read contents of the predetermined memory location.

    Cache miss thread balancing
    34.
    发明专利
    Cache miss thread balancing 未知

    公开(公告)号：GB2574171A8

    公开(公告)日：2019-12-04

    申请号：GB201914312

    申请日：2018-02-27

    Applicant: IBM

    Inventor： GREGORY WILLIAM ALEXANDER ,  SOMIN SONG ,  BRIAN DAVID BARRICK ,  ANTHONY SAPORITO ,  CHRISTIAN JACOBI ,  AARON TSAI ,  THOMAS WINTERS FOX

    IPC: G06F9/38 ,  G06F12/0811

    Abstract: A simultaneous multithread (SMT) processor having a shared dispatch pipeline includes a first circuit that detects a cache miss thread. A second circuit determines a first cache hierarchy level at which the detected cache miss occurred. A third circuit determines a Next To Complete (NTC) group in the thread and a plurality of additional groups (X) in the thread. The additional groups (X) are dynamically configured based on the detected cache miss. A fourth circuit determines whether any groups in the thread are younger than the determined NTC group and the plurality of additional groups (X), and flushes all the determined younger groups from the cache miss thread.

    Cache miss thread balancing
    35.
    发明专利
    Cache miss thread balancing 未知

    公开(公告)号：GB2574171A

    公开(公告)日：2019-11-27

    申请号：GB201914312

    申请日：2018-02-27

    Applicant: IBM

    Inventor： GREGORY WILLIAM ALEXANDER ,  SOMIN SONG ,  BRIAN DAVID BARRICK ,  ANTHONY SAPORITO ,  CHRISTIAN JACOBI ,  AARON TSAI ,  THOMAS WINTERS FOX

    IPC: G06F9/38 ,  G06F12/0811

    Abstract: A simultaneous multithread (SMT) processor having a shared dispatch pipeline includes a first circuit that detects a cache miss thread. A second circuit determines a first cache hierarchy level at which the detected cache miss occurred. A third circuit determines a Next To Complete (NTC) group in the thread and a plurality of additional groups (X) in the thread. The additional groups (X) are dynamically configured based on the detected cache miss. A fourth circuit determines whether any groups in the thread are younger than the determined NTC group and the plurality of additional groups (X), and flushes all the determined younger groups from the cache miss thread.

    Non-quiescing key setting facility
    36.
    发明专利
    Non-quiescing key setting facility 未知

    公开(公告)号：GB2488458B

    公开(公告)日：2017-08-23

    申请号：GB201207328

    申请日：2010-12-14

    Applicant: IBM

    Inventor： TIMOTHY SLEGEL ,  DAN GREINER ,  CHUNG-LUNG KEVIN SHUM ,  CHRISTIAN JACOBI

    IPC: G06F9/30 ,  G06F9/38 ,  G06F12/14

    Abstract: A non-quiescing key setting facility is provided that enables manipulation of storage keys to be performed without quiescing operations of other processors of a multiprocessor system. With this facility, a storage key, which is accessible by a plurality of processors of the multiprocessor system, is updated absent a quiesce of operations of the plurality of processors. Since the storage key is updated absent quiescing of other operations, the storage key may be observed by a processor as having one value at the start of an operation performed by the processor and a second value at the end of the operation. A mechanism is provided to enable the operation to continue, avoiding a fatal exception.

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