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    Programmable High Performance Data Communication Adapter for High Speed Paquet Transmission Networks
    31.
    发明专利
    Programmable High Performance Data Communication Adapter for High Speed Paquet Transmission Networks 未知

    公开(公告)号：CA2120558A1

    公开(公告)日：1994-12-31

    申请号：CA2120558

    申请日：1994-04-05

    Applicant: IBM

    Inventor： GALAND CLAUDE ,  LEBIZAY GERALD ,  MAUDUIT DANIEL ,  MUNIER JEAN-MARIE ,  PAUPORTE ANDRE ,  SAINT-GEORGES ERIC ,  SPAGNOL VICTOR

    IPC: H04L29/06 ,  H04L12/56

    Abstract: A high performance data packet buffering method and a programmable data communication adapter for high speed packet transmission networks are disclosed. The line adapter includes programmable processing means, for receiving and transmitting data packets of fixed or variable length. This system is characterized in that it comprises means for buffering (132) said data packets, means for identifying said buffering means and said data packets in said buffering means, means for queueing (Figure 15) in storing means (131) said identifying means in a single instruction, means for dequeueing (Figure 16) from said storing (131) means said identifying means in another single instruction , means for releasing said buffering means, Each instruction comprises up to three operations executed in parallel by said processing means : an arithmetical and logical (ALU) operation on said identifying means, a memory operation on said storing means, and a sequence operation.

    32.
    发明专利
    未知

    公开(公告)号：DE68918275D1

    公开(公告)日：1994-10-20

    申请号：DE68918275

    申请日：1989-06-29

    Applicant: IBM

    Inventor： LEBIZAY GERALD ,  DEMANGE MICHEL ,  VEDRENNE ALAIN ,  MILEWSKI ANDRZEJ

    IPC: H04Q3/00 ,  H04L12/56

    Abstract: A 3-stage switching system is provided for generating, i.e. finding, reserving and setting, path from one switch entrance port (1) to at least one switch exit port (transmit side) for asynchronously received and buffered data cells. While an Nth cell is being transferred, control means (36) generate a control word including the switch exit port address for cell (N+1)th to be subsequently transferred. Said control word is used to find and reserve a path through the switch on a stage-by-stage basis, and then set said path, if any, using a fed back acknowledgement. The (N+1)th cell path generation is performed during cell N transfer, on a cycle stealing basis.

    37.
    发明专利
    未知

    公开(公告)号：CH600438A5

    公开(公告)日：1978-06-15

    申请号：CH1539775

    申请日：1975-11-27

    Applicant: IBM

    Inventor： BORIE JEAN-CLAUDE ,  COUDER ALAIN ,  DAUBY ALAIN ,  DEMANGE MICHEL ,  LEBIZAY GERALD ,  LECHACZINSKY MICHEL

    IPC: H04Q3/545 ,  G06F1/02 ,  G06F9/46 ,  G06F13/36 ,  G06F13/40 ,  G06F15/80 ,  G06F17/10 ,  H04Q11/04 ,  G06F15/00 ,  G06F15/20

    Abstract: A modular digital signal processor based on a master-slave architecture has the capability of expanding its processing power by aggregating additional modules in a tree type structure. In such a processor the control functions are subdivided into groups, each for performance in a distinct control unit. One or more of the control units can perform a master function with respect to one or several slaved control units and can itself be a slave to a higher level control unit. The arithmetic data functions of the processor are performed in pipe line multiplier-accumulator units (PMAU), each of which is controlled by, instructions from an associated control unit.

    38.
    发明专利
    未知

    公开(公告)号：DE2523372A1

    公开(公告)日：1976-01-15

    申请号：DE2523372

    申请日：1975-05-27

    Applicant: IBM

    Inventor： KERRIGAN MICHAEL ,  LEBIZAY GERALD ,  MACSORLEY OLIN LOWE ,  WEISS ALFRED

    IPC: G06F13/36 ,  G06F13/34 ,  G06F3/04

    Abstract: An input-output port control subsystem for use with a computer system having separate source and destination buses incorporated therein. Said system including circuitry for controlling operations of said system and said input/output subsystem, said subsystem including a bidirectional input/output bus for transferring data to and from said system, and separate gating means for selectively connecting said source and destination buses to said bidirectional I/O bus. External devices are connected to said bus thru an adaptor unit which is directly connected to said processing system by appropriate control lines. The input/output subsystem is adapted to operate either under programmed I/O control mode thru the central processing system or in cycle steal mode wherein the I/O devices themselves request cycle steal service time on the I/O bus thru their connected adaptor.

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