公开(公告)号：DE10030442A1

公开(公告)日：2002-01-17

申请号：DE10030442

申请日：2000-06-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LEHR MATTHIAS ,  TEWS RENE ,  MUELLER JOCHEN ,  LINDOLF JUERGEN

IPC: H01L23/525 ,  H01L23/532 ,  H01L21/28

Abstract: Connecting element consists of a layer structure (1) arranged between two conducting structures. The layer structure is formed by a dielectric layer (2) which can be destroyed by applying a voltage and a silicon layer (3). The dielectric layer borders a first structure made of tungsten. Preferred Features: The dielectric layer is made of Si3N4 or SiO2. The silicon layer is made of amorphous silicon or polysilicon. The first structure made of tungsten is formed from a first conducting pathway (4) with the dielectric layer applied to its upper side.

公开(公告)号：DE10026251A1

公开(公告)日：2001-12-06

申请号：DE10026251

申请日：2000-05-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KAISER ROBERT ,  LINDOLF JUERGEN ,  SCHNEIDER HELMUT ,  SCHAMBERGER FLORIAN

IPC: G11C17/16 ,  H01L23/525 ,  H01L27/105 ,  G11C17/14

Abstract: The fuse or anti-fuse programming device uses application of an electrical voltage (V1-V2) for destruction of the fuse or anti-fuse (1), with the latter connected in series between the source-drain paths of at least 2 transistors (T1,T2), e.g. a p-channel FET and a n-channel FET positioned on opposite sides of the fuse.

公开(公告)号：DE10026243A1

公开(公告)日：2001-12-06

申请号：DE10026243

申请日：2000-05-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KAISER ROBERT ,  LINDOLF JUERGEN ,  SCHNEIDER HELMUT

IPC: G11C17/00 ,  G11C17/18 ,  H01L21/82 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/66 ,  H01L23/525 ,  G11C29/00

Abstract: The fuse state read-out method uses application of a voltage (Vblh) to the fuse which has a reduced voltage level relative to an internal voltage (Vint) of the semiconductor memory device, e.g. a voltage level which is reduced by between 20 and 30 % relative to an internal voltage of about 2 V, for defining the high potential of the bit lines (BL) of the memory cell field (6).

公开(公告)号：DE10014388A1

公开(公告)日：2001-10-04

申请号：DE10014388

申请日：2000-03-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： AYADI KAMEL ,  OEZOGUZ-GEISSLER NEDIM ,  LINDOLF JUERGEN

IPC: G01R31/28 ,  G01R31/316 ,  G11C29/50 ,  G11C29/00 ,  G11C11/4072

Abstract: The method involves producing a memory device with a circuit with two voltage connections and a control input; applying a reference potential (5) to the first voltage connection and a second voltage (8) to the second voltage input; and applying a control voltage (7) to the control input, whereby the control voltage is varied between the reference potential and an operating voltage.

公开(公告)号：DE10255427B4

公开(公告)日：2008-01-17

申请号：DE10255427

申请日：2002-11-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LINDOLF JUERGEN ,  SCHAMBERGER FLORIAN

IPC: H01L21/768 ,  H01L23/525

公开(公告)号：DE10342305A1

公开(公告)日：2005-04-14

申请号：DE10342305

申请日：2003-09-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FISCHER HELMUT ,  LINDOLF JUERGEN ,  SOMMER MICHAEL B

IPC: H01L23/60 ,  H01L27/02 ,  H02H9/00 ,  H02H9/02

Abstract: ESD protection (100) limits voltage heterodyned to useful voltage to permissible level and comprises numerous series-connected diodes (106), which are poled in flow direction, related to useful voltage, with sum of activating voltages of diodes corresponding to permissible voltage. Preferably permissible voltage is of same polarity as useful voltage. Typically number of series-connected diodes is so chosen that permissible voltage is less than blocking voltage of individual diode.

公开(公告)号：DE10131675B4

公开(公告)日：2005-04-07

申请号：DE10131675

申请日：2001-06-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LINDOLF JUERGEN ,  POPP MARTIN ,  SELL BERNHARD

IPC: G01R27/26 ,  G11C29/50 ,  G11C29/00 ,  G01R31/26 ,  G11C11/4076

Abstract: A ring oscillator has a multiplicity of inverters. An interconnect is connected between two of the inverters, and a storage capacitor to be measured, with its associated lead resistor, is coupled to the interconnect either via an interconnect or a transistor can selectively coupled and decouple the capacitor and the lead resistance. A measuring device is connected up to the ring oscillator and is used to determine a value for the oscillation frequency of the ring oscillator on the basis of which a value for the time constant of the storage capacitor can be determined.

公开(公告)号：DE10303963B4

公开(公告)日：2005-02-10

申请号：DE10303963

申请日：2003-01-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KOWALSKI BERNHARD ,  FELBER ANDREAS ,  ROSSKOPF VALENTIN ,  LINDOLF JUERGEN ,  SCHLOESSER TILL ,  GOEBEL BERND

IPC: G11C29/50 ,  G11C29/00

Abstract: The integrated circuit has vertical FET transistors formed in deep channels [DT] as an array of devices. Also formed in the channels are diagonal capacitors. The structure has active semiconductor elements and a conducting strips [BS]. There are bit line contacts [CB] with inputs [E] and outputs [A].

公开(公告)号：DE10332312B3

公开(公告)日：2005-01-20

申请号：DE10332312

申请日：2003-07-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FREY ULRICH ,  LINDOLF JUERGEN ,  FELBER ANDREAS

IPC: H01L23/525

Abstract: The integrated semiconductor circuit (20) has a programmable switch element (10) switched between an off state and an on state by supplying a positive programming voltage (V+) to a counter-electrode (5) of the switch element, separated from a substrate electrode (2) within a substrate (1) held at a substrate potential (Vo) via an insulation layer (8). The substrate electrode is supplied with a negative programming voltage (V-) during programming of the switch element, a current barrier layer (7) preventing a current flow between the substrate electrode and the substrate.

公开(公告)号：DE10303963A1

公开(公告)日：2004-08-19

申请号：DE10303963

申请日：2003-01-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KOWALSKI BERNHARD ,  FELBER ANDREAS ,  ROSSKOPF VALENTIN ,  LINDOLF JUERGEN ,  SCHLOESSER TILL ,  GOEBEL BERND

IPC: G11C29/50 ,  G11C29/00

Abstract: The integrated circuit has vertical FET transistors formed in deep channels [DT] as an array of devices. Also formed in the channels are diagonal capacitors. The structure has active semiconductor elements and a conducting strips [BS]. There are bit line contacts [CB] with inputs [E] and outputs [A].