31.
    发明专利
    未知

    公开(公告)号:DE59814220D1

    公开(公告)日:2008-05-29

    申请号:DE59814220

    申请日:1998-01-27

    Abstract: A field effect-controllable semiconductor component, such as a new IGBT using planar technology, includes a shielding zone disposed about a base zone, resulting in elevation of a minority charge carrier density at a cathode side of the IGBT, leading to a reduction of forward voltage. The effect of a drift field produced due to a concentration gradient between the shielding zone and the base zone is that the inner zone no longer acts as a sink for the minority charge carriers. In order to ensure that the breakdown voltage of the IGBT is not reduced by the incorporation of the shielding zone, a non-connected, floating region of high conductivity is disposed in the region of the inner zone. A lower edge of the non-connected, floating region is deeper in the inner zone than a lower edge of the shielding zone. The non-connected, floating region has a conduction type opposite that of the shielding zone and the inner zone.

    35.
    发明专利
    未知

    公开(公告)号:DE102004007197A1

    公开(公告)日:2005-09-01

    申请号:DE102004007197

    申请日:2004-02-13

    Abstract: A semiconductor component having a drift path ( 2 ) which is formed in a semiconductor body ( 1 ), is composed of a semiconductor material of first conductance type. The drift path ( 2 ) is arranged between at least one first and one second electrode ( 3, 4 ) and has a trench structure in the form of at least one trench ( 18 ). A dielectric material which is referred to as a high-k material and has a relative dielectric constant epsilon r where epsilon r >=20 is arranged in the trench structure such that at least one high-k material region ( 5 ) and one semiconductor material region ( 6 ) of the first conductance type are arranged in the area of the drift path ( 2 ).

    39.
    发明专利
    未知

    公开(公告)号:DE10246960B4

    公开(公告)日:2004-08-19

    申请号:DE10246960

    申请日:2002-10-09

    Abstract: An FE power transistor comprises two semiconductor regions (10,12) with MOS channels, source/drain connections, gate control contacts (10',12') and a control connection (16). An overvoltage protection unit (13) between the second gate and drain connects to the second semiconductor region if a gate/drain threshold voltage is exceeded.

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