公开(公告)号：DE10394006T5

公开(公告)日：2005-11-17

申请号：DE10394006

申请日：2003-12-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WELLHAUSEN UWE ,  HILLIGER ANDREAS ,  NAGEL NICOLAS ,  BRUCHHAUS RAINER ,  GERNHARDT STEFAN ,  LIAN JING YU

IPC: H01L21/8246 ,  H01L23/00 ,  H01L21/02 ,  H01L21/8239 ,  H01L21/84 ,  H01L27/105

公开(公告)号：DE10131627A1

公开(公告)日：2003-01-30

申请号：DE10131627

申请日：2001-06-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRUCHHAUS RAINER ,  ENDERS GERHARD ,  HARTNER WALTER ,  KROENKE MATTHIAS ,  MIKOLAJICK THOMAS ,  NAGEL NICOLAS ,  ROEHNER MICHAEL

IPC: H01L21/02 ,  H01L21/8246 ,  H01L27/115 ,  H01L27/11502 ,  H01L27/11507 ,  H01L21/8239 ,  H01L27/105

Abstract: Semiconductor memory has capacitor devices (10-1,...., 10-4) each vertically extending from a substrate (20) and/or a passivating region (21) and/or a surface region (20a). A three dimensional arrangement or structure is formed for each capacitor device. An Independent claim is also included for a process for the production of a semiconductor memory. Preferred Features: The capacitor devices each have a first electrode arrangement (14), a second electrode arrangement (18) with a dielectric (16) arranged between the arrangements. The capacitor devices are a stacked structure of form part of a stacked structure.

公开(公告)号：DE10131624A1

公开(公告)日：2003-01-23

申请号：DE10131624

申请日：2001-06-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRUCHHAUS RAINER ,  ENDERS GERHARD ,  HARTNER WALTER ,  KROENKE MATTHIAS ,  MIKOLAJICK THOMAS ,  NAGEL NICOLAS ,  ROEHNER MICHAEL

IPC: H01L21/02 ,  H01L21/8246 ,  H01L27/115 ,  H01L27/11502 ,  H01L27/11507 ,  H01L27/105 ,  H01L21/8239

Abstract: A method for manufacturing a semiconductor memory device, in which a semiconductor substrate (20) a passivation zone (21) and/or a surface zone (20a, 21a) are designed with a CMOS structure. The capacitor device (10-1...10-4) is structured mainly in the horizontally-extending semiconductor substrate or similar of a passivation zone (21) and/or a surface zone from it, at least partly and/or locally structured and mainly vertically formed. A passivation zone (21) and/or a surface zone (20a, 21a) is formed and/or structured at least partly in the arrangement or structure extending in the third dimension for the respective capacitor device (10-1...10-4). An Independent claim is given for a chain-FeRAM store. (B)

公开(公告)号：DE10131492A1

公开(公告)日：2003-01-16

申请号：DE10131492

申请日：2001-06-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRUCHHAUS RAINER ,  ENDERS GERHARD ,  HARTNER WALTER ,  KROENKE MATTHIAS ,  MIKOLAJICK THOMAS ,  NAGEL NICOLAS ,  ROEHNER MICHAEL

IPC: G11C7/00 ,  H01L21/02 ,  H01L21/8239 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11502 ,  H01L27/11507

Abstract: Production of a semiconductor device comprises forming and/or structuring capacitor arrangements (10-1, ..., 10-4) on a semiconductor substrate (20), a passivating region (21) and/or surface region (20a, 21a), and forming a three-dimensional arrangement for the capacitor arrangements. An Independent claim is also included for the semiconductor device produced by the above process. Preferred Features: Electrode arrangements (14, 18) and a dielectric (16) of each capacitor arrangement are formed and/or structured on the substrate, passivating region and/or surface region.

公开(公告)号：DE102005053509A1

公开(公告)日：2007-04-05

申请号：DE102005053509

申请日：2005-11-09

Applicant: INFINEON TECHNOLOGIES AG

Inventor： OLLIGS DOMINIK ,  MIKOLAJICK THOMAS ,  DEPPE JOACHIM ,  MUELLER TORSTEN ,  NAGEL NICOLAS ,  BACH LARS ,  POLEI VERONIKA ,  BOUBEKEUR HOCINE

IPC: H01L21/8239 ,  G11C5/06 ,  H01L21/768 ,  H01L21/8247

Abstract: In a process to manufacture a semiconductor product, word guides are positioned above the substrate in a first direction (X) at intervals parallel to the substrate surface (22). Contact structures and first filling structures are formed between the word guides. The contact structures are of a defined width along the first direction (X) and are separated by the first filling structure. A mask is formed with apertures in a second direction (y) parallel to the substrate surface (22). The contact structures are wet-etched through the apertures (12) and the resulting detents are filled with a second agent (5), followed by formation of the bit guides that make contact with the structure (3) along the second direction.

公开(公告)号：DE102005037029A1

公开(公告)日：2007-01-11

申请号：DE102005037029

申请日：2005-08-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： OLLIGS DOMINIK ,  MIKOLAJICK THOMAS ,  NAGEL NICOLAS ,  BACH LARS ,  POLEI VERONIKA ,  MUELLER TORSTEN

IPC: H01L21/8247 ,  G11C16/02

Abstract: A semiconductor product includes, a substrate with a first dielectric layer having contact hole fillings for contacting active areas in the substrate. A second dielectric layer with contact holes is provided therein. The contact holes have a width in a first lateral direction. The product further includes conductive lines, each conductive line passing over contact holes in the second dielectric layer and contacting a plurality of contact hole fillings in the first dielectric layer. The conductive lines have a width, in the first lateral direction, that is smaller than the width of the contact holes of the second dielectric layer. The conductive lines are in direct mechanical contact with the contact hole fillings and thereby remove the need to provide any conventional "contact to interconnect" structures.

公开(公告)号：DE10131627B4

公开(公告)日：2006-08-10

申请号：DE10131627

申请日：2001-06-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRUCHHAUS RAINER ,  ENDERS GERHARD ,  HARTNER WALTER ,  KROENKE MATTHIAS ,  MIKOLAJICK THOMAS ,  NAGEL NICOLAS ,  ROEHNER MICHAEL

IPC: H01L21/8239 ,  H01L21/02 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11502 ,  H01L27/11507

Abstract: Capacitor devices are formed in an essentially vertically extending fashion in order to achieve an essentially three-dimensional configuration or a configuration extending into the third dimension. A contacting of plug regions is performed after producing the capacitor devices. Such capacitor devices provide an increased integration density in a semiconductor memory device.

公开(公告)号：DE19958200B4

公开(公告)日：2006-07-06

申请号：DE19958200

申请日：1999-12-02

Applicant: INFINEON TECHNOLOGIES AG

Inventor： NAGEL NICOLAS ,  PRIMIG ROBERT ,  KASKO IGOR ,  BRUCHHAUS RAINER

IPC: H01L23/532 ,  H01L21/02 ,  H01L21/285 ,  H01L21/321 ,  H01L21/8242 ,  H01L27/105

Abstract: A microelectronic structure has an adhesion layer which is disposed between a base substrate and a barrier layer. The adhesion layer improves the adhesion of the barrier layer on the base substrate, in particular to insulation layers provided there. Microelectronic structures of this type are preferably used in semiconductor memories. A method of fabricating such a microelectronic structure is also provided.

公开(公告)号：DE10152636A1

公开(公告)日：2003-01-30

申请号：DE10152636

申请日：2001-10-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KROENKE MATTHIAS ,  BRUCHHAUS RAINER ,  ENDERS GERHARD ,  HARTNER WALTER ,  MIKOLAJICK THOMAS ,  NAGEL NICOLAS ,  ROEHNER MICHAEL

IPC: H01L21/02 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/108 ,  H01L27/115 ,  H01L27/11502 ,  H01L27/11507

Abstract: Semiconductor memory has capacitor devices (10-1,...., 10-4) each vertically extending from a substrate (20) and/or a passivating region (21) and/or a surface region (20a). A three dimensional arrangement or structure is formed for each capacitor device. An Independent claim is also included for a process for the production of a semiconductor memory. Preferred Features: The capacitor devices each have a first electrode arrangement (14), a second electrode arrangement (18) with a dielectric (16) arranged between the arrangements. The capacitor devices are a stacked structure of form part of a stacked structure.

公开(公告)号：DE10131626A1

公开(公告)日：2003-01-30

申请号：DE10131626

申请日：2001-06-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KROENKE MATTHIAS ,  BRUCHHAUS RAINER ,  ENDERS GERHARD ,  HARTNER WALTER ,  MIKOLAJICK THOMAS ,  NAGEL NICOLAS ,  ROEHNER MICHAEL

IPC: H01L21/02 ,  H01L21/768 ,  H01L21/8246 ,  H01L27/115 ,  H01L27/11502 ,  H01L27/11507 ,  H01L21/8239

Abstract: Production of a semiconductor memory comprises forming a semiconductor substrate (20), a passivating region (21) and/or a surface region (20a,21a) having a CMOS structure; forming capacitor arrangements (10-1, ..., 10-4) in the region of the substrate, passivating region and/or surface region; and providing first and second contact regions or plug regions (P1, P2) to contact with the capacitor arrangements. Preferred Features: The contact regions or plug regions are formed after forming the CMOS structure. Each capacitor arrangement has a first lower or bottom electrode device (14), a second upper or top electrode arrangement (18), and a dielectric (16) formed between the two electrode arrangements.