公开(公告)号：CA2343741C

公开(公告)日：2009-01-13

申请号：CA2343741

申请日：1999-09-03

Applicant: QUALCOMM INC

Inventor： ZOU QUIZHEN ,  SIH GILBERT C

IPC: G01S19/03 ,  G01S1/00 ,  G01S19/48 ,  H04Q7/34 ,  H04W64/00

Abstract: The present invention is a novel and improved method and apparatus for performing position location in wireless communications system. One embodiment of the invention comprises a method of performing position location in a wireless subscriber unit having a local oscillator, including the steps of receiving a position location request, acquiring a timing signal when a sufficient period of time has elapsed since the local oscillator has been corrected and correcting said local oscillator using a correction signal based on said timing signal, substantially freezing the connection signal, performing a position location procedure using the local oscillator with the correction signal applied, and ending said position location procedure.

公开(公告)号：DE69924867T2

公开(公告)日：2006-03-02

申请号：DE69924867

申请日：1999-11-18

Applicant: QUALCOMM INC

Inventor： ZOU QUIZHEN ,  SIH C ,  AGRAWAL AVNEESH

IPC: G06F7/58 ,  H03K3/84 ,  H04B1/707 ,  H04B7/26 ,  H04J13/00 ,  H04J13/10

Abstract: A novel and improved method and apparatus for a fast-slewing pseudorandom noise sequence generator is described. One or more loadable PN generators are controlled by a DSP or microprocessor in conjunction with a free-running counter which maintains a reference offset count. The PN generator will typically be part of a finger or searcher. The DSP or microprocessor may assist in other finger or searcher functions as well as the slew function, and can control one or more fingers and/or searchers. Each PN generator is comprised of a loadable linear feedback shift register (LFSR) or its equivalent, a loadable counter for maintaining an index of the state of that particular PN generator, and a slew control device capable of receiving a slew command and controlling the LFSR and index counter to enact an advance or a retard of a certain offset distance.

公开(公告)号：DE69925720D1

公开(公告)日：2005-07-14

申请号：DE69925720

申请日：1999-03-04

Applicant: QUALCOMM INC

Inventor： SIH C ,  ZOU QUIZHEN ,  JHA K ,  KANG INYUP ,  LIN JIAN ,  MOTIWALA QUAEED ,  JOHN DEEPU ,  ZHANG LI ,  ZHANG HAITAO ,  LEE WAY-SHING ,  SAKAMAKI E ,  KANTAK A

IPC: G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F12/08 ,  G06F12/0886 ,  G06F15/78

Abstract: A circuit for digital signal processing calls for the use of a variable length instruction set. An exemplary DSP includes a set of three data buses (108, 110, 112) over which data may be exchanged with a register bank (120) and three data memories (102, 103, 104). A register bank (120) may be used that has registers accessible by at least two processing units (128, 130). An instruction fetch unit (156) may be included that receives instructions of variable length stored in an instruction memory (152). The instruction memory (152) may be separate from the set of three data memories (102, 103, 104).

公开(公告)号：HK1035594A1

公开(公告)日：2001-11-30

申请号：HK01106221

申请日：2001-09-04

Applicant: QUALCOMM INC

Inventor： SIH GILBERT C ,  ZOU QUIZHEN ,  JHA SANJAY K ,  KANG INYUP ,  LIN JIAN ,  MOTIWALA QUAEED ,  JOHN DEEPU ,  ZHANG LI ,  ZHANG HAITAO ,  LEE WAY-SHING ,  SAKAMAKI CHARLES E ,  KANTAK PRASHANT A

IPC: G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F12/08 ,  G06F12/0886 ,  G06F15/78

Abstract: A circuit for digital signal processing calls for the use of a variable length instruction set. An exemplary DSP includes a set of three data buses (108, 110, 112) over which data may be exchanged with a register bank (120) and three data memories (102, 103, 104). A register bank (120) may be used that has registers accessible by at least two processing units (128, 130). An instruction fetch unit (156) may be included that receives instructions of variable length stored in an instruction memory (152). The instruction memory (152) may be separate from the set of three data memories (102, 103, 104).

公开(公告)号：AU4251400A

公开(公告)日：2000-10-16

申请号：AU4251400

申请日：2000-03-30

Applicant: QUALCOMM INC

Inventor： AGRAWAL AVNEESH ,  ZOU QUIZHEN

IPC: H04B1/7093 ,  H04B1/7075 ,  H04B1/7077 ,  H04B1/708 ,  H04B1/707

Abstract: A novel and improved method and apparatus for searching is described. Channel data is despread utilizing a matched filter structure. The in-phase and quadrature amplitudes of the despreading delivered to coherent accumulators to sum for a programmable duration of time. The amplitude accumulations are squared and summed to produce an energy measurement. The energy measurement is accumulated for a second programmable time to perform non-coherent accumulation. The resulting value is used to determine the likelihood of a pilot signal at that offset. Each matched filter structure comprises an N-value shift register for receiving data, a programmable bank of taps to perform despreading and optional Walsh decovering, and an adder structure to sum the resulting filter tap calculations.

公开(公告)号：AU6027699A

公开(公告)日：2000-03-27

申请号：AU6027699

申请日：1999-09-03

Applicant: QUALCOMM INC

Inventor： SIH GILBERT C ,  ZOU QUIZHEN

IPC: G01S19/03 ,  G01S1/00 ,  G01S19/48 ,  H04Q7/34 ,  G01S5/00 ,  G01S5/14

Abstract: The present invention is a novel and improved method and apparatus for performing position location in wireless communications system. One embodiment of the invention comprises a method of performing position location in a wireless subscriber unit having a local oscillator, including the steps of receiving a position location request, acquiring a timing signal when a sufficient period of time has elapsed since the local oscillator has been corrected and correcting said local oscillator using a correction signal based on said timing signal, substantially freezing the correction signal, performing a position location procedure using the local oscillator with the correction signal applied, and ending said position location procedure.

公开(公告)号：AU2986099A

公开(公告)日：1999-10-11

申请号：AU2986099

申请日：1999-03-04

Applicant: QUALCOMM INC

Inventor： SIH GILBERT C ,  ZOU QUIZHEN ,  JHA SANJAY K ,  KANG INYUP ,  LIN JIAN ,  MOTIWALA QUAEED ,  JOHN DEEPU ,  ZHANG LI ,  ZHANG HAITAO ,  LEE WAY-SHING ,  SAKAMAKI CHARLES E ,  KANTAK PRASHANT A

IPC: G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F12/08 ,  G06F12/0886 ,  G06F15/78

Abstract: A circuit for digital signal processing calls for the use of a variable length instruction set. An exemplary DSP includes a set of three data buses (108, 110, 112) over which data may be exchanged with a register bank (120) and three data memories (102, 103, 104). A register bank (120) may be used that has registers accessible by at least two processing units (128, 130). An instruction fetch unit (156) may be included that receives instructions of variable length stored in an instruction memory (152). The instruction memory (152) may be separate from the set of three data memories (102, 103, 104).

公开(公告)号：CA2324219A1

公开(公告)日：1999-09-23

申请号：CA2324219

申请日：1999-03-04

Applicant: QUALCOMM INC

Inventor： SAKAMAKI CHARLES E ,  KANTAK PRASHANT A ,  SIH GILBERT C ,  LEE WAY-SHING ,  ZHANG HAITAO ,  ZHANG LI ,  JOHN DEEPU ,  ZOU QUIZHEN ,  JHA SANJAY K ,  KANG INYUP ,  LIN JIAN ,  MOTIWALA QUAEED

IPC: G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F12/08 ,  G06F12/0886 ,  G06F15/78

Abstract: A circuit for digital signal processing calls for the use of a variable length instruction set. An exemplary DSP includes a set of three data buses (108, 110, 112) over which data may be exchanged with a register bank (120) and three data memories (102, 103, 104). A register bank (120) may be used that has registers accessible by at least two processing units (128, 130). An instruction fetch unit (156) may be included that receives instructions of variable length stored in an instruction memory (152). The instruction memory (152) may be separate from the set of three data memories (102, 103, 104).

公开(公告)号：AU2009200172A1

公开(公告)日：2009-02-12

申请号：AU2009200172

申请日：2009-01-16

Applicant: QUALCOMM INC

Inventor： WILEY GEORGE ALAN ,  STEELE BRIAN ,  ZOU QUIZHEN

IPC: H04L29/00 ,  H04J3/06 ,  H04L12/56 ,  H04L12/64 ,  H04L29/08 ,  H04N7/08 ,  H04N7/081

公开(公告)号：HK1094608A1

公开(公告)日：2007-04-04

申请号：HK07101408

申请日：2001-09-04

Applicant: QUALCOMM INC

Inventor： SIH GILBERT C ,  ZOU QUIZHEN ,  JHA SANJAY K ,  KANG INYUP I ,  LIN JIAN ,  MOTIWALA QUAEED ,  JOHN DEEPU ,  ZHANG LI ,  ZHANG HAITAO ,  LEE WAY-SHING ,  SAKAMAKI CHARLES E ,  KANTAK PRASHANT A

IPC: G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F12/08 ,  G06F12/0886 ,  G06F15/78

Abstract: A circuit for digital signal processing calls for the use of a variable length instruction set. An exemplary DSP includes a set of three data buses (108, 110, 112) over which data may be exchanged with a register bank (120) and three data memories (102, 103, 104). A register bank (120) may be used that has registers accessible by at least two processing units (128, 130). An instruction fetch unit (156) may be included that receives instructions of variable length stored in an instruction memory (152). The instruction memory (152) may be separate from the set of three data memories (102, 103, 104).