公开(公告)号：DE69229734T2

公开(公告)日：2000-03-02

申请号：DE69229734

申请日：1992-10-30

Applicant: ST MICROELECTRONICS SRL

Inventor： TOMASINI LUCIANO ,  CASTELLO RINALDO

IPC: H03H7/06 ,  H03H7/00 ,  H03H11/34 ,  H03H11/36 ,  H04M1/60 ,  H04M1/76

Abstract: A monolithically integrated AC coupler comprising two capacitors, C1 and C2, respectively connected between an input terminal Vin and an output terminal Vout, and between one said output terminal and a first terminal of connection to a reference potential Vref1. Connected in parallel with the capacitor C1, and serially together, are a capacitor C3 and two field-effect transistors, M1 and M2. Two field-effect transistors, M3 and M4, are connected between the output terminal and a second terminal of connection to a reference potential, Vref2. The connection nodes between the transistors M1 and M2 and between the transistors M3 and M4 are coupled, through two capacitors CS1 and CS2, to the first connection terminal Vref1. The gate terminals of the transistors are applied control signals with two non-overlapping phases, F1 and F2.

公开(公告)号：ITRM20000032D0

公开(公告)日：2000-01-20

申请号：ITRM20000032

申请日：2000-01-20

Applicant: ST MICROELECTRONICS SRL

Inventor： TOMASINI LUCIANO ,  GUINEA JESUS ,  CASTELLO RINALDO

IPC: G05F3/24 ,  G05F3/26

Abstract: The generator includes complementary MOS transistors interconnected in four circuit branches one of which contains a constant-current generator. Voltages picked up at various nodes of the circuit can be used as reference and/or biasing voltages of the integrated circuit, which account for the variability of the manufacturing parameters.

公开(公告)号：DE69229734D1

公开(公告)日：1999-09-09

申请号：DE69229734

申请日：1992-10-30

Applicant: ST MICROELECTRONICS SRL

Inventor： TOMASINI LUCIANO ,  CASTELLO RINALDO

IPC: H03H7/06 ,  H03H7/00 ,  H03H11/34 ,  H03H11/36 ,  H04M1/60 ,  H04M1/76

Abstract: A monolithically integrated AC coupler comprising two capacitors, C1 and C2, respectively connected between an input terminal Vin and an output terminal Vout, and between one said output terminal and a first terminal of connection to a reference potential Vref1. Connected in parallel with the capacitor C1, and serially together, are a capacitor C3 and two field-effect transistors, M1 and M2. Two field-effect transistors, M3 and M4, are connected between the output terminal and a second terminal of connection to a reference potential, Vref2. The connection nodes between the transistors M1 and M2 and between the transistors M3 and M4 are coupled, through two capacitors CS1 and CS2, to the first connection terminal Vref1. The gate terminals of the transistors are applied control signals with two non-overlapping phases, F1 and F2.

公开(公告)号：DE69226021T2

公开(公告)日：1998-10-22

申请号：DE69226021

申请日：1992-09-23

Applicant: ST MICROELECTRONICS SRL

Inventor： TOMASINI LUCIANO ,  CASTELLO RINALDO ,  CONFALONIERI PIERANGELO

IPC: H03K17/06 ,  H03K17/687

Abstract: A driver circuit for an electronic switch (2) which is to be operated from a clock signal (F) having a predetermined frequency, comprises an input pin (A) being applied the clock signal, and a voltage doubler (1) connected between said pin (A) and the switch (2).

公开(公告)号：DE69631772D1

公开(公告)日：2004-04-08

申请号：DE69631772

申请日：1996-12-04

Applicant: ST MICROELECTRONICS SRL

Inventor： REZZI FRANCESCO ,  CASTELLO RINALDO ,  CAZZANIGA MARCO ,  BIETTI IVAN

IPC: H03H11/04

Abstract: The invention relates to an elementary biquadratic cell for programmable time-continous analog filters, which is placed between a first supply voltage reference (Vdd) and a second voltage reference (GND) and is of a type having at least one pair of input terminals (I31,I31') and first (O31,O31') and second (O32,O32') pairs of output terminals, and having a pair of half-cells (31,31'), which half-cells are structurally identical with each other and each comprised of at least a first transistor (T31,T31') placed between the first (Vdd) and the second (GND) voltage reference and having a base terminal connected to a respective one of the input terminals (I31,I31'). Each half-cell (31,31') further comprises second (T32,T32') and third (T33,T33') transistors placed between the first (Vdd) and second (GND) voltage references, the second transistor (T32,T32') having a base terminal connected to the first output terminal (O31,O31') of the first pair of output terminals and a collector terminal connected to the second output terminal (O32,O32') of the second pair of output terminals, and the third transistor (T33,T33') having an emitter terminal connected to the first output terminal (O31,O31') of the first pair of output terminals ad a base terminal connected to the second output terminal (O32',O32) of the second pair of output terminals of the other half-cell.

公开(公告)号：IT1320380B1

公开(公告)日：2003-11-26

申请号：ITTO20000493

申请日：2000-05-26

Applicant: ST MICROELECTRONICS SRL

Inventor： BASCHIROTTO ANDREA ,  CUSINATO PAOLO ,  MONTAGNA GIAMPIERO ,  CASTELLO RINALDO

IPC: H03F3/00 ,  H03F3/45

Abstract: A switched operational amplifier with fully differential topology, alternately switchable on and off, and a control circuit. The operational amplifier has a first differential output (4a) and a second differential output, and a control terminal. The control circuit includes a capacitive detecting network including a first capacitor and a second capacitor connected between the first and second differential outputs and a common-mode node, and a third capacitor connected between the common-mode node and ground in a first operative condition, and between the common-mode node and the supply voltage in a second operative condition. A control transistor is connected between the common-mode node and the control terminal of the operational amplifier and supplies a control current correlated to the voltage on the common-mode node. A switchable voltage source, connected to the common-mode node, supplies a desired voltage in a first operative condition, when the operational amplifier is off.

公开(公告)号：DE69530773D1

公开(公告)日：2003-06-18

申请号：DE69530773

申请日：1995-10-30

Applicant: ST MICROELECTRONICS SRL

Inventor： TOMASINI LUCIANO ,  CASTELLO RINALDO ,  CLERICI GIANCARLO ,  BIETTI IVAN

IPC: H03K17/06

Abstract: The interface circuit described is disposed between a generator (LG) of control signals (CS) and a plurality of electronic switches (SW) in order to produce boosted voltage signals (SCS) corresponding to the control signals (CS) for activating the electronic switches (SW). To avoid the use of capacitors with high capacitance and thus to save area of the integrated circuit, the circuit comprises a generator (SCK) of boosted-voltage clock signals ( phi , phi ) and a plurality of voltage multipliers (VM) each having an input connected to an output of the control signal generator (LG), an output connected to at least one terminal for activating an electronic switch (SW) and two control terminals connected to the boosted-voltage clock-signal generator.

公开(公告)号：DE69529908D1

公开(公告)日：2003-04-17

申请号：DE69529908

申请日：1995-11-30

Applicant: ST MICROELECTRONICS SRL

Inventor： TOMASINI LUCIANO ,  CASTELLO RINALDO ,  CLERICI GIANCARLO ,  BIETTI IVAN

IPC: H03F1/08 ,  H03F1/14 ,  H03F1/34 ,  H03F1/00

Abstract: An operational amplifier frequency self-compensated with respect to closed-loop gain comprises a transconductance input stage (2) and an amplifier output stage (3) connected serially together to receive an input signal (Sin) on at least one input terminal (IN) of the amplifier and generate an amplified signal (Sout) on an output terminal (OUT) of the amplifier. Provided between the input (2) and output (3) stages is an intermediate node (S) which is connected to a compensation block (11) to receive a frequency-variable compensation signal (Sc) therefrom. According to the invention, the compensation block (11) is coupled with its input to the input terminal (IN) of the amplifier. The compensation block (11) is connected to receive at least the feedback signal (Sf). Preferably, the compensation signal (Sc) is variable as a function of a gain value (Gcl) which is determined by the feedback circuit, and said variation of the compensation signal occurs in a relationship of inverse proportionality to the gain value. This invention is useful in discrete circuits whose operational amplifier forms a device by itself, as well as in fully integrated circuits.

公开(公告)号：DE69428888T2

公开(公告)日：2002-07-04

申请号：DE69428888

申请日：1994-06-30

Applicant: ST MICROELECTRONICS SRL

Inventor： REZZI FRANCESCO ,  BASCHIROTTO ANDREA ,  CASTELLO RINALDO

IPC: H03F3/45

Abstract: The transconductor system in accordance with the present invention is the type comprising a first transconductor circuit (C1) having differential mode transconductance equal to a first value and common mode transconductance equal to a second value and is characterised in that it comprises a second transconductor circuit (C2) connected in parallel with said transconductor circuit (C1) having common mode transconductance substantially equal in modulus to said second value and of opposite sign. In this manner the common mode current signal at the output is greatly reduced.

公开(公告)号：DE69427471T2

公开(公告)日：2002-04-25

申请号：DE69427471

申请日：1994-07-29

Applicant: ST MICROELECTRONICS SRL

Inventor： PISATI VALERIO ,  ALINI ROBERTO ,  CASTELLO RINALDO ,  VAI GIANFRANCO

IPC: H03F3/343 ,  H03F3/45 ,  H03G1/00 ,  H03H11/24 ,  H03F1/08 ,  H03H11/04