公开(公告)号：ITMI910836D0

公开(公告)日：1991-03-28

申请号：ITMI910836

申请日：1991-03-28

Applicant: CONS RIC MICROELETTRONICA ,  SGS THOMSON MICROELECTRONICS

Inventor： FRISINA FERRUCCIO ,  FERLA GIUSEPPE

IPC: H01L21/22 ,  H01L29/73 ,  H01L21/322 ,  H01L21/331 ,  H01L21/8222 ,  H01L27/07 ,  H01L27/082 ,  H01L29/732 ,  H01L29/861 ,  H01L

Abstract: The structure consists of a single chip (1) of semiconductor material, which comprises an area (32) having a high lifetime of the minority carriers, which constitutes a bipolar power device with high current density, and at least one area (20, 21; 20', 21') with a reduced lifetime of the minority carriers, which constitutes a fast diode.

公开(公告)号：JP2000138232A

公开(公告)日：2000-05-16

申请号：JP28383899

申请日：1999-10-05

Applicant: ST MICROELECTRONICS SRL

Inventor： FRISINA FERRUCCIO ,  FERLA GIUSEPPE

IPC: G11C29/14 ,  G11C29/50 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a power device which does not raise problems related to threshold voltage, even if a normal insulating material is used for forming an insulating spacer and will not raise strain causing dislocations or cracks in silicon, even if another material such as silicon nitride is used. SOLUTION: This power semiconductor device has a second insulating material region 10 positioned at a side part of a polysilicon layer 5 and a first insulating material region 6, and at the upper side of a region 14 positioned near the opening at the upper side of an insulation layer body region 2 of a gate oxide layer 4, an oxide region 9 formed between a polysilicon region 5 and the second insulating material region 10, and an oxide spacer 8 formed in the upper side of a second material region.

公开(公告)号：DE69324003D1

公开(公告)日：1999-04-22

申请号：DE69324003

申请日：1993-06-28

Applicant: CONS RIC MICROELETTRONICA

Inventor： FRISINA FERRUCCIO ,  COFFA SALVATORE

IPC: H01L21/331 ,  H01L29/06 ,  H01L29/167 ,  H01L29/73 ,  H01L29/732

Abstract: There is described a bipolar power transistor with high breakdown voltage, obtained in a heavily doped semiconductor substrate (1) of the N type over which a lightly doped N type layer (2), constituting a collector region of the transistor, is superimposed; the transistor has a base region comprising a heavily doped P type diffusion (4) which extends into the lightly doped N type layer (2) from a top surface, and an emitter region constituted by a heavily doped N type diffusion (11) extending from said top surface within said heavily doped P type diffusion (4); the heavily doped P type diffusion (4) is obtained within a deep lightly doped P type diffusion (3), extending from said top surface into the lightly doped N type layer (2) and formed with acceptor impurities represented by atoms of aluminium.

公开(公告)号：IT9022237D0

公开(公告)日：1990-11-29

申请号：IT2223790

申请日：1990-11-29

Applicant: CONS RIC MICROELETTRONICA

Inventor： FRISINA FERRUCCIO ,  TAVOLO NELLA ,  RASPAGLIESI MARIO

IPC: H01L21/322 ,  H01L21/22 ,  H01L21/265 ,  H01L21/336 ,  H01L29/78 ,  H01L

公开(公告)号：JP2003152160A

公开(公告)日：2003-05-23

申请号：JP2002316673

申请日：2002-10-30

Applicant: ST MICROELECTRONICS SRL

Inventor： FRISINA FERRUCCIO ,  PINTO ANTONIO ,  MAGLI ANGELO

IPC: H01L25/07 ,  H01L23/48 ,  H01L23/485 ,  H01L23/495 ,  H01L25/18 ,  H01L29/417

Abstract: PROBLEM TO BE SOLVED: To improve electric connection between an electronic power device and a package and avoid the formation of an uncontrollable chemical composition area. SOLUTION: The electronic power device (1) having an improved structure is manufactured by employing MOS technique so as to have at least one gate finger area (3) and related source areas (4) positioned at both sides of the area (3). The electronic power device is provided with at least first level metallic layers (3', 4') arranged so as to be contacted individually with the gate finger area and the source areas, and a passivation layer (5) for protection which is arranged so as to cover the gate finger area. A wetting metallic layer (7) is advantageous to be built up on the passivation layer and the first level metallic layer (4') for covering the source area. According to this method, an additional wetting metallic layer functions as a second level metallic layer.

公开(公告)号：JP2000058829A

公开(公告)日：2000-02-25

申请号：JP13955599

申请日：1999-05-20

Applicant: ST MICROELECTRONICS SRL

Inventor： MAGRI ANGELO ,  FRISINA FERRUCCIO

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide the structure of a high density MOS technology power device provided with a first conductivity-type base area formed in a second conductivity-type semiconductor layer. SOLUTION: A base area has at least pairs of substantially linear and substantially parallel base stripes 32. The respective base stripes 32 are connected to the adjacent base stripes 32 at end parts by a junction area. Thus, at least the pairs of base stripes 32 and the junction area can form continuous meandered base areas 31A-31D.

公开(公告)号：DE69421606T2

公开(公告)日：2000-05-31

申请号：DE69421606

申请日：1994-03-30

Applicant: CONS RIC MICROELETTRONICA

Inventor： FRISINA FERRUCCIO

IPC: H01L29/73 ,  H01L21/22 ,  H01L21/331 ,  H01L29/732

Abstract: A manufacturing process for obtaining integrated structure bipolar transistors with controlled storage time comprises the steps of: in a silicon material (1, 2), forming at least one bipolar transistor occupying a first area (AD) on a first surface of the silicon material (1, 2); covering the first surface of the silicon material (1, 2) with an insulating material layer (5); selectively removing the insulating material layer (5) to open at least one window (6) having a second area (APt) much smaller than the first area (AD) occupied by the bipolar transistor; implanting into the silicon material (1, 2) a medium dose (D) of platinum ions through said window (6); and diffusing into the silicon material (1, 2) the implanted platinum ions to obtain a uniform distribution of platinum inside the transistor.

公开(公告)号：IT1245365B

公开(公告)日：1994-09-20

申请号：ITMI910836

申请日：1991-03-28

Applicant: CONS RIC MICROELETTRONICA ,  SGS THOMSON MICROELECTRONICS

Inventor： FRISINA FERRUCCIO ,  FERLA GIUSEPPE

IPC: H01L21/22 ,  H01L29/73 ,  H01L21/322 ,  H01L21/331 ,  H01L21/8222 ,  H01L27/07 ,  H01L27/082 ,  H01L29/732 ,  H01L29/861 ,  H01L

Abstract: The structure consists of a single chip (1) of semiconductor material, which comprises an area (32) having a high lifetime of the minority carriers, which constitutes a bipolar power device with high current density, and at least one area (20, 21; 20', 21') with a reduced lifetime of the minority carriers, which constitutes a fast diode.

公开(公告)号：JP2000183348A

公开(公告)日：2000-06-30

申请号：JP34999899

申请日：1999-12-09

Applicant: ST MICROELECTRONICS SRL

Inventor： FRISINA FERRUCCIO

IPC: H01L21/336 ,  H01L29/06 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a MOS gate power device with low output resistance. SOLUTION: A MOS gate power device is provided with plural element function units. The element function units are provided with first conductivity- type main body regions 3 formed in second conductivity-type semiconductor material layers 2, 21, 22 and 23. Plural first conductivity-type impurity addition regions 20, 201 and 202 are formed in the semiconductor material layers 2, 21, 22 and 23, and the impurity addition regions 20, 201 and 202 are arranged below the respective main body regions 3 and are detached from the adjacent impurity addition regions by the semiconductor material layers 2, 21, 22 and 23.

公开(公告)号：JP2000164841A

公开(公告)日：2000-06-16

申请号：JP28993099

申请日：1999-10-12

Applicant: ST MICROELECTRONICS SRL

Inventor： POLMAN ALBERT ,  HAMELIN NICHOLAS ,  KIK PETER ,  COFFA SALVATORE ,  FRISINA FERRUCCIO ,  SAGGIO MARIO

IPC: H01L31/108 ,  G01J1/02 ,  G02B6/12 ,  H01L27/14 ,  H01L31/0352 ,  H01L31/103

Abstract: PROBLEM TO BE SOLVED: To obtain an infrared detector device, exhibiting a high efficiency of transfer from infrared radiation to electrical currents by a semiconductor material. SOLUTION: An infrared detector device 1 is provided with P-N junctions 9 and 10, comprised of a first semiconductor material region 9 doped with rare-earth ions and a second semiconductor material region 10 of the oppositely doped type P. The detector device extends on a substrate 2, including a reflection layer 4 and is provided with a wave guide path 8 formed by protrusions whose range in horizontal direction is demarcated by an oxide a region for protection and containment. At least a part of the wave guide path 8 is formed of a P-N junction and has an end to which light to be detected is supplied. The detector device has electrodes 18 and 13, placed on the side and top of the wave guide path 8 and enables efficient collection of charge carriers produced by optical transfer.