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公开(公告)号：DE69421072D1
公开(公告)日：1999-11-11
申请号：DE69421072
申请日：1994-05-23
Applicant: ST MICROELECTRONICS SRL
Inventor： ZUFFADA MAURIZIO , GADDUCCI PAOLO , MOLONEY DAVID , PISATI VALERIO
Abstract: The device is to be used with a parallel architecture PRML reading apparatus comprising a variable-gain input amplifier (21), a low-pass analog filter (22), a transversal analog filter (23) and two distinct and parallel processing channels (24, 34) interposed between the transversal analog filter (23) and an RLL-NRZ decoder (25). The two processing channels (24, 34) comprise respective analog-digital converters (26, 36) and respective Viterbi detectors (27, 37) and operate according to sampling sequences that alternate with one another. The device (30) for processing the servo signals comprises a rectifier (31) connected to the outputs of said analog-digital converters (26, 36) and an integrator (32).
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公开(公告)号：IT1316796B1
公开(公告)日：2003-05-12
申请号：ITMI20000469
申请日：2000-03-09
Applicant: ST MICROELECTRONICS SRL
Inventor： PISATI VALERIO , DEMICHELI MARCO , BRUCCOLERI MELCHIORRE
Abstract: A circuit device for restoring the symmetry of an analog signal originated by the reading of data from magnetic supports, including at least one differential cell multiplier whose cell includes a pair of input MOS transistors having respective conduction terminals linked together at a circuit node. Advantageously, provided in parallel with each of the cell input transistors, are a plurality of transistors individually connectable to and disconnectable from each of the input transistors by corresponding switches.
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公开(公告)号：IT1316690B1
公开(公告)日：2003-04-24
申请号：ITMI20000393
申请日：2000-02-29
Applicant: ST MICROELECTRONICS SRL
Inventor： PISATI VALERIO , PORTALURI SALVATORE , CAZZANIGA MARCO , CASTELLO RINALDO
Abstract: This invention relates to a circuit structure of the feedforward type with programmable zeroes, particularly for synthesizing time-continual filters. This structure comprises a pair of amplification cells (14,15) interconnected at at least one interconnection node (A) and connected between a first signal (Vin) input (IN) of a first cell (14) and an output terminal (U) of the second cell (15, each cell (14,15) comprising a pair of transistors (10,2;6,7) which have a conduction terminal in common and have the other conduction terminals coupled respectively to a first voltage reference (Vcc) through respective bias members (3,4;9,11). The structure further comprises a circuit leg (13) connecting a node (X) of the first cell (14) to the output terminal (U) and comprising a transistor (8) which has a control terminal connected to the node (X) of the first cell (14), a first conduction terminal connected to the output terminal (U), and a second conduction terminal coupled to a second voltage reference (GND) through a capacitor (Cc). Thus, a released "zero" can be introduced in the right semiplane of the pole-zero complex plane to improve the flattening of group gain.
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公开(公告)号：IT1316688B1
公开(公告)日：2003-04-24
申请号：ITMI20000391
申请日：2000-02-29
Applicant: ST MICROELECTRONICS SRL
Inventor： VENCA ALESSANDRO , PISATI VALERIO , CAZZANIGA MARCO
Abstract: The invention relates to a low supply voltage analog multiplier which comprises a pair of differential cells (10,11), each cell comprising a pair of bipolar transistors (2,3;6,7) with coupled emitters. A first transistor (2,6) of each cell (10,11) receives an input signal (Vin+,Vin-) on its base terminal and has its collector terminal coupled to a first voltage reference (Vcc) through a bias member (4,8). Advantageously, the second transistor (3,7) of each cell is a diode configuration, and the cells are interconnected at a common node (A) corresponding to the base terminals of the second transistors (3,7) in each pair. This multiplier can be supplied very low voltages and still exhibit a high rate of operation along with reduced harmonic distortion of the output signal, even with input signals of peak-to-peak amplitude above 600 mV.
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公开(公告)号：DE69710593D1
公开(公告)日：2002-03-28
申请号：DE69710593
申请日：1997-12-23
Applicant: ST MICROELECTRONICS SRL
Inventor： PORTALURI SALVATORE , PISATI VALERIO
Abstract: A feedforward structure with programmable zeros for synthesizing continuous-time filters, delay lines and the like, whose particularity is that it comprises a first cell and a second cell which are cascade-connected, each one of the first and second cells comprising a first pair (1, 2) of bipolar transistors in which the emitter terminals are connected to a current source (5), the first pair of transistors being connected to a second pair of transistors (6, 7), a current source (11) being connected to the emitter terminals of the second pair of transistors, a first high-impedance element (C) being connected between the first and second pairs of transistors, a second high-impedance element (C) being connected in output to the second pair of transistors, a fifth transistor (8) being connected between the collector terminal of a first transistor (1) of the first pair of transistors and a collector terminal of a second transistor (2) of the second pair of transistors, the base terminal of the fifth transistor (8) receiving a signal which is taken from the collector terminal of the first transistor of the first pair of transistors and is taken with a positive sign in the first cell and with a negative sign in the second cell, in order to determine a transfer function with a pair of singularities at the numerator, the second transistors (2, 7) of the first and second pairs being controlled respectively by current sources (4, 9) which have mutually different values.
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Patent Agency Ranking
公开(公告)号：DE69427479T2
公开(公告)日：2002-01-17
申请号：DE69427479
申请日：1994-11-30
Applicant: ST MICROELECTRONICS SRL
Inventor： BRIANTI FRANCESCO , PISATI VALERIO , ALINI ROBERTO , MOLONEY DAVID
IPC: G05F3/26
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公开(公告)号：ITMI20000393A1
公开(公告)日：2001-08-29
申请号：ITMI20000393
申请日：2000-02-29
Applicant: ST MICROELECTRONICS SRL
Inventor： CASTELLO RINALDO , PORTALURI SALVATORE , PISATI VALERIO , CAZZANIGA MARCO
Abstract: This invention relates to a circuit structure of the feedforward type with programmable zeroes, particularly for synthesizing time-continual filters. This structure comprises a pair of amplification cells (14,15) interconnected at at least one interconnection node (A) and connected between a first signal (Vin) input (IN) of a first cell (14) and an output terminal (U) of the second cell (15, each cell (14,15) comprising a pair of transistors (10,2;6,7) which have a conduction terminal in common and have the other conduction terminals coupled respectively to a first voltage reference (Vcc) through respective bias members (3,4;9,11). The structure further comprises a circuit leg (13) connecting a node (X) of the first cell (14) to the output terminal (U) and comprising a transistor (8) which has a control terminal connected to the node (X) of the first cell (14), a first conduction terminal connected to the output terminal (U), and a second conduction terminal coupled to a second voltage reference (GND) through a capacitor (Cc). Thus, a released "zero" can be introduced in the right semiplane of the pole-zero complex plane to improve the flattening of group gain.
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公开(公告)号：ITMI20000391A1
公开(公告)日：2001-08-29
申请号：ITMI20000391
申请日：2000-02-29
Applicant: ST MICROELECTRONICS SRL
Inventor： PISATI VALERIO , VENCA ALESSANDRO , CAZZANIGA MARCO
Abstract: The invention relates to a low supply voltage analog multiplier which comprises a pair of differential cells (10,11), each cell comprising a pair of bipolar transistors (2,3;6,7) with coupled emitters. A first transistor (2,6) of each cell (10,11) receives an input signal (Vin+,Vin-) on its base terminal and has its collector terminal coupled to a first voltage reference (Vcc) through a bias member (4,8). Advantageously, the second transistor (3,7) of each cell is a diode configuration, and the cells are interconnected at a common node (A) corresponding to the base terminals of the second transistors (3,7) in each pair. This multiplier can be supplied very low voltages and still exhibit a high rate of operation along with reduced harmonic distortion of the output signal, even with input signals of peak-to-peak amplitude above 600 mV.
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公开(公告)号：DE69231151D1
公开(公告)日：2000-07-13
申请号：DE69231151
申请日：1992-08-26
Applicant: ST MICROELECTRONICS SRL
Inventor： CASTELLO RINALDO , ALINI ROBERTO , REZZI FRANCESCO , PISATI VALERIO
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公开(公告)号：ITMI20000469D0
公开(公告)日：2000-03-09
申请号：ITMI20000469
申请日：2000-03-09
Applicant: ST MICROELECTRONICS SRL
Inventor： BRUCCOLERI MELCHIORRE , PISATI VALERIO , DEMICHELI MARCO
Abstract: A circuit device for restoring the symmetry of an analog signal originated by the reading of data from magnetic supports, including at least one differential cell multiplier whose cell includes a pair of input MOS transistors having respective conduction terminals linked together at a circuit node. Advantageously, provided in parallel with each of the cell input transistors, are a plurality of transistors individually connectable to and disconnectable from each of the input transistors by corresponding switches.
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