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    Method and system for correcting errors during read and write to non volatile memories
    31.
    发明公开
    Method and system for correcting errors during read and write to non volatile memories 审中-公开
    非易失性存储器的写入和读取过程中的方法和系统差错更正

    公开(公告)号：EP1612950A1

    公开(公告)日：2006-01-04

    申请号：EP04425486.0

    申请日：2004-06-30

    Applicant: STMicroelectronics S.r.l.

    Inventor： Marelli, Alessia ,  Ravasio, Roberto ,  Micheloni, Rino

    IPC: H03M13/15 ,  G06F11/10

    CPC classification number: H03M13/1555 ,  H03M13/152 ,  H03M13/6561

    Abstract: The invention relates to a method and system for correcting errors in multilevel memories, both of the NAND and of the NOR type. The method provides the use of a BCH correction code made parallel by means of a coding and decoding architecture allowing the latency limits of prior art sequential solutions to be overcome. Two possible solutions are shown.
    The parallelism being used for blocks C, 1 and 3 can be chosen in order to optimise the system performances in terms of latency and device area.

    Abstract translation: 本发明涉及一种方法和系统，用于多级存储器校正错误，这两种类型的NAND和NOR。 该方法提供使用的BCH纠错码由编码和解码架构，允许现有技术解决方案的顺序的延迟限制的方式作出平行于被克服。 两种可能的解决方案中。 正在使用的并行用于块C，1和3可以以优化系统性能的延迟和设备面积方面进行选择。

    Method for performing error corrections of digital information codified as a symbol sequence
    33.
    发明公开
    Method for performing error corrections of digital information codified as a symbol sequence 审中-公开
    Fehlerkorrekturmethodefürals Symbolsequenz codierte digitale Daten

    公开(公告)号：EP1460765A1

    公开(公告)日：2004-09-22

    申请号：EP03425172.8

    申请日：2003-03-19

    Applicant: STMicroelectronics S.r.l.

    Inventor： Lunelli, Massimiliano ,  Micheloni, Rino ,  Ravasio, Roberto ,  Marelli, Alessia

    IPC: H03M13/13 ,  H03M13/15 ,  H03M13/19

    CPC classification number: H03M13/1575 ,  H03M13/13 ,  H03M13/15 ,  H03M13/19

    Abstract: A method for making error corrections on digital information coded as symbol sequences ( x ), for example digital information stored in electronic memory systems or transmitted from and to these systems is described, providing the transmission of sequences ( x ) incorporating a portion of error corrector code allowing the sequence ( x ) which is more probably the original transmitted through the calculation of an error syndrome using a parity matrix to be restored when received.
    Advantageously according to the invention, the error code incorporated in the original sequence ( x ) belongs to a non Boolean group.

    Abstract translation: 描述了用于对编码为符号序列（x）的数字信息进行纠错的方法，例如存储在电子存储器系统中或从这些系统发送的数字信息，或从这些系统发送和传送到这些系统的方法，提供包含错误校正器的一部分的序列（x） 允许更可能是通过使用奇偶校验矩阵计算误差校正子传送的序列（x）的序列（x），以便在接收时恢复。 有利地，根据本发明，并入原始序列（x）中的错误代码属于非布尔组。

    power supply circuit structure for a row decoder of a multilevel non-volatile memory device
    34.
    发明公开
    power supply circuit structure for a row decoder of a multilevel non-volatile memory device 有权
    多功能三极管

    公开(公告)号：EP1434233A1

    公开(公告)日：2004-06-30

    申请号：EP02029093.8

    申请日：2002-12-30

    Applicant: STMicroelectronics S.r.l.

    Inventor： Micheloni, Rino ,  Campardo, Giovanni

    IPC: G11C11/56

    CPC classification number: G11C11/5621 ,  G11C8/14 ,  G11C11/56 ,  G11C16/08 ,  G11C16/30

    Abstract: The invention relates to a power supply circuit structure useful with a row decoder for reading/writing data from/into memory cells of an integrated electrically programmable/erasable non-volatile memory device incorporating an array of multilevel memory cells. Advantageously, multiple supply voltages to the row decoder and switching means for transferring said voltages over hierarchic-mode enabled conduction paths are provided.

    Abstract translation: 本发明涉及一种与行解码器有用的电源电路结构，用于从包含多电平存储器单元的阵列的集成电可编程/可擦除非易失性存储器件读/写存储单元的数据。 有利地，提供了对于行解码器和切换装置的多个电源电压，用于在分层模式使能的传导路径上传送所述电压。

    Self-repair method for non volatile memory device with erasing/programming failure detection, and non volatile memory device therefor
    37.
    发明公开
    Self-repair method for non volatile memory device with erasing/programming failure detection, and non volatile memory device therefor 有权
    用于与擦除/编程错误检测非易失性存储器件和非易失性存储器设备，用于自修复方法

    公开(公告)号：EP1365419A1

    公开(公告)日：2003-11-26

    申请号：EP02425319.7

    申请日：2002-05-21

    Applicant: STMicroelectronics S.r.l.

    Inventor： Micheloni, Rino ,  Losavio, Aldo

    IPC: G11C29/00

    CPC classification number: G11C29/82 ,  G11C29/846

    Abstract: The memory device (20) has a memory block (1), formed by a plurality of standard sectors (15) and a redundancy portion (2); a control circuit (3), which controls programming and erasing of the data of the memory cells; and a correctness verifying circuit (7) for the data stored in the memory cells. The correctness verifying circuit (7) is enabled by the control circuit (3) and generates an incorrect-datum signal in the event of detection of at least one non-functioning cell. The control circuit moreover activates redundancy, enabling the redundancy portion (2) and storing redundancy data in a redundancy-memory stage (5b) in the presence of an incorrect datum. Various solutions are presented that implement column, row and sector redundancy, both in case of erasing and programming.

    Abstract translation: 所述存储器装置（20）具有存储块（1）中，通过标准的扇区（15）的形成有多个和冗余部（2）; 其控制所述存储器单元的数据的编程和擦除控制电路（3）; 和用于所述数据的正确性验证电路（7）存储在存储器单元中。 正确性验证电路（7）由所述控制电路（3）和基因速率不正确的，基准信号在检测到至少一个非功能性细胞的的情况下启用。 该控制电路更在激活冗余，使冗余部分（2）和在一个不正确的日期的存在下，在冗余存储器阶段（5b）中存储的冗余数据。 各种解决方案都没有实现列，行和部门冗余，无论是在擦除和编程的情况。

    Self-repair method for nonvolatile memory devices using a supersecure architecture, and nonvolatile memory device
    39.
    发明公开
    Self-repair method for nonvolatile memory devices using a supersecure architecture, and nonvolatile memory device 有权
    与架构非易失性存储器，用于避免错误和非易失性存储器的自修复方法

    公开(公告)号：EP1357559A1

    公开(公告)日：2003-10-29

    申请号：EP02425265.2

    申请日：2002-04-26

    Applicant: STMicroelectronics S.r.l.

    Inventor： Micheloni, Rino ,  Losavio, Aldo

    IPC: G11C29/00

    CPC classification number: G11C29/808

    Abstract: The self-repair method for a nonvolatile memory (1) intervenes at the end of an operation of modification, selected between programming and erasing, in the event of detection of just one non-functioning cell (14a, 14c), and carries out redundancy of the non-functioning cell. To this end, the memory array (15) is divided into a basic portion (20), formed by a plurality of memory cells (14a) storing basic data, and into a on-the-field redundancy portion (21), said on-the-field redundancy portion (21) being designed to store redundancy data including a correct content of the non-functioning cell, the address of the non-functioning cell, and an activated redundancy flag. The redundancy is activated only after applying a preset maximum number of modification pulses and uses a purposely designed redundancy replacement circuit (12) and a purposely designed redundancy data verification circuit (7b).

    Abstract translation: 用于非易失性存储器（1）的自修复方法介入在操作修改的结束时，编程和擦除之间选择，在检测只有一个无功能的细胞（14A，14C）的的情况下，进行冗余 的非功能性细胞。 为此，存储器阵列（15）被划分成基本部分（20），由存储器单元的存储基本数据的多个（14a）的形成，并且为上的场冗余部分（21），所述上 -the场冗余部分（21）被设计来存储数据冗余包括无功能的细胞的正确的内容，无功能单元的地址，以及在活化的冗余标志。 冗余只施加变形脉冲的预置最大数之后被激活，并使用一个专门设计冗余置换电路（12）和一个专门设计的冗余数据的验证电路（7B）。

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