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    Process for manufacturing a non-volatile memory cell
    31.
    发明公开
    Process for manufacturing a non-volatile memory cell 审中-公开
    制造的只读存储单元的方法

    公开(公告)号：EP1179839A2

    公开(公告)日：2002-02-13

    申请号：EP01114948.1

    申请日：2001-06-20

    Applicant: STMicroelectronics S.r.l.

    Inventor： Bez, Roberto ,  Camerlenghi, Emilio ,  Ratti Stefano

    IPC: H01L21/336 ,  H01L21/8247

    CPC classification number: H01L27/11521 ,  H01L27/115

    Abstract: A process for fabricating non-volatile memory cells on a semiconductor substrate comprises the following steps:

    forming a stack structure comprised of a first polysilicon layer (3) isolated from the substrate by an oxide layer (2);
    cascade etching the first polysilicon layer (3), oxide layer (2), and semiconductor substrate (1) to define a first portion of a floating gate region of the cell and at least one trench (6) bordering an active area (AA) of the memory cell;
    filling the at least one trench (6) with an isolation layer (7);
    depositing a second polysilicon layer (8) onto the whole exposed surface of the semiconductor; and
    etching away the second polysilicon layer (8) to expose the floating gate region formed in the first polysilicon layer (3), thereby forming extensions (9) adjacent to the above portion of the first polysilicon layer (3).

    Phase-change memory device and manufacturing process thereof
    35.
    发明公开
    Phase-change memory device and manufacturing process thereof 有权
    法新社 - 佛罗伦萨

    公开(公告)号：EP1684352A1

    公开(公告)日：2006-07-26

    申请号：EP05425024.6

    申请日：2005-01-21

    Applicant: STMicroelectronics S.r.l.

    Inventor： Zuliani, Paola ,  Pellizzer, Fabio ,  Bez, Roberto

    IPC: H01L27/24 ,  H01L45/00 ,  G11C11/34

    CPC classification number: H01L27/2436 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144

    Abstract: Phase-change memory device, wherein memory cells (2) are arranged in rows (7) and columns (6) and form a memory array. The memory cells (2) are formed by a selection device (4) of an MOS type and by a phase-change region (3) connected to the selection device. The selection device (4) is formed by a first conductive region (32) and a second conductive region (33), which extend in a substrate (31) of semiconductor material and are spaced from one another via a channel region (34), and by an isolated control region (36) connected to a respective row (7) and overlying the channel region (34). The first conductive region (32) is connected to a connection line (42) extending parallel to the rows, the second conductive region (33) is connected to the phase-change region (46), and the phase-change region is connected to a respective column (6). The first connection line (42) is a metal interconnection line and is connected to the first conductive region (32) via a source-contact region (40) made as point contact and distinct from the first connection line (42).

    Abstract translation: 相变存储器件，其中存储器单元（2）以行（7）和列（6）排列并形成存储器阵列。 存储单元（2）由MOS型的选择装置（4）和连接到选择装置的相变区域（3）形成。 选择装置（4）由在半导体材料的衬底（31）中延伸并且经由沟道区（34）彼此间隔开的第一导电区域（32）和第二导电区域（33）形成， 以及连接到相应行（7）并且覆盖通道区域（34）的隔离控制区域（36）。 第一导电区域（32）连接到与行平行延伸的连接线（42），第二导电区域（33）连接到相变区域（46），相变区域连接到 相应的列（6）。 第一连接线（42）是金属互连线，并且经由源点接触区域（40）与第一导电区域（32）连接，源极接触区域（40）形成为与第一连接线（42）不同的点接触。

    Process for manufactoring integrated resistive elements with silicidation protection
    36.
    发明公开
    Process for manufactoring integrated resistive elements with silicidation protection 审中-公开
    Verfahren zur Herstellung integrierter Widerstandselemente mit Silizidationsschutz

    公开(公告)号：EP1403909A1

    公开(公告)日：2004-03-31

    申请号：EP02425586.1

    申请日：2002-09-30

    Applicant: STMicroelectronics S.r.l.

    Inventor： Grossi, Alessandro ,  Bez, Roberto ,  Servalli, Giorgio

    IPC: H01L21/02 ,  H01L27/08

    CPC classification number: H01L28/20 ,  H01L27/0802

    Abstract: A process for the fabrication of integrated resistive elements with protection from silicidation envisages the steps of: delimiting, in a semiconductor wafer (10), at least one active area (15); and forming, in the active area (15) at least one resistive region (21) having a pre-determined resistivity. Prior to forming the resistive region (21), on top of the active area (15) a delimitation structure (20) for delimiting the resistive region (21) is obtained, and, subsequently, protective elements (25), which extend within the delimitation structure (20) and coat the resistive region (21), are obtained.

    Abstract translation: 集成电阻器通过在半导体晶片（10）中限定至少一个有效区域来制造; 以及在所述有源区域中形成具有预设电阻率的电阻区域。 在有源区域的顶部，形成用于限定电阻区域的定界结构。 获得了在限定结构内延伸并覆盖电阻区域的保护元件。

    Nonvolatile memory cell with high programming efficiency
    37.
    发明公开
    Nonvolatile memory cell with high programming efficiency 有权
    NichtflüchtigeSpeicherzelle mit hoher Programmierungsleistung

    公开(公告)号：EP1178540A1

    公开(公告)日：2002-02-06

    申请号：EP00830546.8

    申请日：2000-07-31

    Applicant: STMicroelectronics S.r.l.

    Inventor： Esseni, David ,  Selmi, Luca ,  Bez, Roberto ,  Modelli, Alberto

    IPC: H01L29/788 ,  H01L27/115

    CPC classification number: H01L29/66825 ,  G11C16/0416 ,  H01L27/11521 ,  H01L29/7885

    Abstract: The memory cell (1) is formed in a body (3) of a P-type semiconductor material forming a channel region (25) and housing N-type drain and source regions (15, 12) at two opposite sides of the channel region (25). A floating gate region (5) extends above the channel region (25). A P-type charge injection region (18) extends in the body (3) contiguously to the drain region (15), at least in part between the channel region (25) and the drain region (15). An N-type base region (21) extends between the drain region (15), the charge injection region (18), and the channel region (25). The charge injection region (18) and the drain region (15) are biased by special contact regions (19, 16) so as to forward bias the PN junction formed by the charge injection region (18) and the base region (21). The holes thus generated in the charge injection region (18) are directly injected through the base region (21) into the body (3), where they generate, by impact, electrons that are injected towards the floating gate region (5).

    Abstract translation: 存储单元（1）形成在形成沟道区域（25）的P型半导体材料的主体（3）中，并且在沟道区域的两个相对侧容纳N型漏极和源极区域（15,12） （25）。 浮动栅极区域（5）在沟道区域（25）的上方延伸。 P型电荷注入区域（18）至少部分地在沟道区域（25）和漏极区域（15）之间连续延伸到漏极区域（15）。 N型基极区域（21）在漏极区域（15），电荷注入区域（18）和沟道区域（25）之间延伸。 电荷注入区域（18）和漏极区域（15）被特殊接触区域（19,16）偏置，以便对由电荷注入区域（18）和基极区域（21）形成的PN结进行正向偏压。 这样在电荷注入区域（18）中产生的空穴通过基极区域（21）直接注入到体（3）中，在那里它们通过冲击产生被注入到浮动栅极区域（5）的电子。

    Methode of making a non-volatile MOS semiconductor memory device
    40.
    发明公开
    Methode of making a non-volatile MOS semiconductor memory device 审中-公开
    HerstellungsverfahrenfürFestwert-MOS-Halbleiterspeicherbauelement

    公开(公告)号：EP1675181A1

    公开(公告)日：2006-06-28

    申请号：EP04425937.2

    申请日：2004-12-22

    Applicant: STMicroelectronics S.r.l.

    Inventor： Tessariol, Paolo ,  Bez, Roberto

    IPC: H01L27/115 ,  H01L21/8247 ,  H01L21/28 ,  H01L29/423

    CPC classification number: H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42336

    Abstract: A method of making a non-volatile MOS semiconductor memory device includes a formation phase, in a semiconductor material substrate (50), of STI isolation regions (shallow trench isolation) (57) filled by field oxide (65) and of memory cells (500) separated each other by said STI isolation regions (57). The memory cells (500) include a gate electrode (52) electrically isolated from said semiconductor material substrate (50) by a first dielectric layer (53), and the gate electrode includes a floating gate (54) self-aligned to the STI isolation regions (57). The method includes a formation phase of said floating gate (54) exhibiting a substantially saddle shape including a concavity; the formation phase of said floating gate (54) includes a deposition phase of a first conformal conductor material layer (54A).

    Abstract translation: 一种制造非易失性MOS半导体存储器件的方法包括在半导体材料衬底（50）中由场氧化物（65）填充的STI隔离区域（浅沟槽隔离）（57））和存储器单元（ 500）通过所述STI隔离区域（57）彼此分离。 存储单元（500）包括通过第一介电层（53）与所述半导体材料基板（50）电隔离的栅电极（52），并且所述栅电极包括与所述STI隔离自对准的浮栅（54） 地区（57）。 该方法包括所述浮动栅极（54）的形成阶段，其显示包括凹部的基本鞍形; 所述浮置栅极（54）的形成阶段包括第一共形导体材料层（54A）的沉积阶段。

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