公开(公告)号：JPH11186200A

公开(公告)日：1999-07-09

申请号：JP34664497

申请日：1997-12-16

Applicant: UNITED MICROELECTRONICS CORP

Inventor： YO MEISEI ,  WU JUAN-YUAN ,  RO KATETSU ,  SUN SHIH-WEI

IPC: H01L21/304 ,  C09K3/14 ,  H01L21/321

Abstract: PROBLEM TO BE SOLVED: To enable CMP process of tungsten with the same polishing pad and the same polishing station, by polishing a dielectric layer after polishing process of a metal layer, and setting pH values of first slurry mixed solution and second slurry mixed solution in the respective specified ranges. SOLUTION: In a process, a chemically/mechanically polishing method is contained, a dielectric layer is formed, and at least one via of a through hole is formed in the dielectric layer. A tungsten layer is formed in the via and on the dielectric layer. In order to eliminate the tungsten layer form the dielectric layer, first slurry 42 having oxidizing component whose pH value is about 2-4 is used, and first chemically/mechanically polishing process is performed. By using second slurry whose pH value is about 2-4, second chemically/ mechanically polishing processing is performed, and the dielectric layer is polished.

公开(公告)号：JPH11176953A

公开(公告)日：1999-07-02

申请号：JP2299898

申请日：1998-02-04

Applicant: UNITED MICROELECTRONICS CORP

Inventor： CHUNG CHENG-HUI ,  SHENG YI-CHUNG

IPC: H01L27/112 ,  H01L21/8246

Abstract: PROBLEM TO BE SOLVED: To form ROM having four threshold voltages and to store multi-bit data in a single memory unit by manufacturing a double layer structure memory transistor sharing the same gate oxide layer through the use of the manufacture technology of a thin film transistor. SOLUTION: A first photo resist layer 37 is formed so that it covers a semiconductor substrate 300, and a first coding step is executed. Then, second area/ third areas of a channel area 320 are doped. A thin film transistor oxide layer 39 is formed on the substrate 300 and a second polycrystalline silicon layer 41 which is doped in P-type is formed on the substrate 300. A second polycrystalline silicon layer 41 is doped by N-type dopant by using a photo mask 43. A second photo resist layer 44 is formed on the thin film transistor and a second coding step is executed. Thus, four state mask ROM is manufactured by such two coding steps.

公开(公告)号：JPH11163260A

公开(公告)日：1999-06-18

申请号：JP30673497

申请日：1997-11-10

Applicant: UNITED MICROELECTRONICS CORP

Inventor： YEW TRI-RUNG ,  RO KATETSU ,  SUN SHIH-WEI

IPC: H01L27/04 ,  H01L21/822

Abstract: PROBLEM TO BE SOLVED: To increase the charge conservation capability of an integrated-circuit capacitor, which can be utilized in a memory, and to provided increased conservation capability even though the manufacturing cost is decreased at the same time. SOLUTION: This method is for forming the increased capacitance for the charge conservation structure of an integrated-circuit device and includes the following processes. In a first process, access circuits 16 and 18, which control access to the electrode of the charge conservation structure through an electrode contact 22, are formed on a substrate 10. In a second process, a first conducting layer 36 is formed on a substrate 10 under the contact state with the electrode contact 22. In a third process, a dielectric material layer 42 is formed on the first conducting layer 36. In a fourth process, the layer of polysilicon particles 40 is formed on the dielectric material layer 42, and a non-covered part is made to remain between the particles. In a fifth process, these exposed parts of the dielectric material layer 42 are selectively removed, and column bodies 42 of the dielectric material are formed with an interval which is provided on these columnar bodies 42. In a sixth process, a second conducting layer 44 is formed on these columnar bodies 42. In a seventh process, a capacitor layer 44 is formed on these columnar bodies 42. In a eigth process, a capacitor dielectric layer 46 is formed on the second dielectric layer 44. In a last process, a third dielectric layer 50 is formed on the capacitor dielectric layer 46.

公开(公告)号：JPH11121718A

公开(公告)日：1999-04-30

申请号：JP1051198

申请日：1998-01-22

Applicant: UNITED MICROELECTRONICS CORP

Inventor： YEW TRI-RUNG ,  RO KATETSU ,  SUN SHIH-WEI ,  SHIH HSUEH-HAO

IPC: C23C16/04 ,  C23C16/24 ,  H01L21/02 ,  H01L21/205 ,  H01L21/285 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To obtain the capacitor storage node of an integrated circuit by a method wherein the title semispherical silicon crystalline particle structure is selectively formed by the chemical vapor phase synthetic process producing a by-product using chlorosilane as a precursor. SOLUTION: A substrate 20 having silicon oxide layers 24 and a contact hole 22 passing through them 24 is prepared while the contact hole 22 is filled up with polycystalline silicon so as to form a contact plug. After the formation of a polycrystalline silicon layer 26 on the contact hole 22 and the silicon oxide layers 24, the polycrystalline silicon layer 26 is patterned to form a lower part electrode. Next, silicon crystalline particles are grown using chlorosilane as a precursor. At this time the nuclear growth of silicon on the polycrystalline silicon layer 26 rapidly advances while the etching away speed of silicon by HCl is slower than that of HSG-Si structure but the silicon nuclear growth on the silicon oxide layers 24 takes a long time thereby raking the formation of the HSG-Si structure selectable.

公开(公告)号：JPH11121434A

公开(公告)日：1999-04-30

申请号：JP944998

申请日：1998-01-21

Applicant: UNITED MICROELECTRONICS CORP

Inventor： CHO GIGUN ,  RIN KENTEI ,  CHIN SHINRAI

IPC: H01L21/302 ,  H01L21/3065

Abstract: PROBLEM TO BE SOLVED: To provide an etching method which increases etching selectivity between oxide and metal silicide and simplifies the etching process itself. SOLUTION: An etching gas of the same composition and the same flow rate is used for a major etching process wherein an opening 50 is formed on an oxide layer 49 and for an over etching process. The etching gas contains CO. More specifically, the etching gas mixture that contains CHF3 , CF4 , argon and CO is used and the flow rate of each gas is 10-50, 10-50, 100-500 and 100-300 SCCM(standard cubic centimeter per minute).

公开(公告)号：JPH1168052A

公开(公告)日：1999-03-09

申请号：JP21521897

申请日：1997-08-08

Applicant: UNITED MICROELECTRONICS CORP

Inventor： SUN SHIH-WEI ,  SAI MOKIN

IPC: H01L27/08

Abstract: PROBLEM TO BE SOLVED: To form a gate oxide of different thickness easily on a single chip by implanting a dopant into a first region and a dopant of different dosage into a second region thereby growing an oxide in the first region and an oxide of different thickness in the second region. SOLUTION: Nitrogen ions are implanted into the surface of a substrate in section A through a pad-like oxide layer 26 until a dosage of about 5×10 /cm is reached, for example. The silicon surface in section A implanted with nitrogen ions is then exposed to an oxidizing atmosphere and a gate oxide layer of about 40Å is grown on the surface of the substrate. Subsequently, nitrogen ions are implanted into section B of the substrate 10 through the exposed pad-like oxide layer 26. Nitrogen ions are implanted at a dosage of 2×10 /cm , for example. Subsequently, the silicon surface in section B implanted with nitrogen ions is exposed to an oxidizing atmosphere and a gate oxide layer of about 75Å is formed.

公开(公告)号：JPH1167621A

公开(公告)日：1999-03-09

申请号：JP21519797

申请日：1997-08-08

Applicant: UNITED MICROELECTRONICS CORP

Inventor： SE SHAKURYU

IPC: G03F7/039 ,  C08G73/00 ,  G03F7/40 ,  H01L21/027

Abstract: PROBLEM TO BE SOLVED: To prevent pattern registration errors and to improve overlay accuracy by forming a gate oxide layer, a conductive layer and a resist layer in sequence by lamination on a substrate and by forming an electrical charge dissipating layer including a specified conductive polymer on the resist layer. SOLUTION: A gate oxide layer is formed on a silicon substrate 10. A conductive layer such as polysilicon is formed on the gate oxide layer and is subjected to patterning for demarcating suitable gate electrodes for use in device manufacture. An electron-beam resist layer 12 is deposited on the conductive layer and an electrical charge dissipating layer 14 including a conductive polymer represented by a formula is deposited on the resist layer 12. In this case, R is acid in the formula. In this way, arising of pattern registration errors can be prevented and the overlay accuracy can be improved.

公开(公告)号：JPH1117170A

公开(公告)日：1999-01-22

申请号：JP944798

申请日：1998-01-21

Applicant: UNITED MICROELECTRONICS CORP

Inventor： SAI MOKIN

IPC: H01L29/78

Abstract: PROBLEM TO BE SOLVED: To solve the problem of irregular reflection by providing a polysilicon layer and a gate comprising a noncrystal layer on the polysilicon layer on a gate structure. SOLUTION: A gate structure has a gate 340 of the double-layer structure. The gate 340 is formed on a silicon oxide layer 310 on a silicon substrate 300 by photoengraving technology. The gate 340 comprises a polysilicon layer 320 and noncrystal silicon layer 330. The noncrystal silicon 330 is formed on the polysilicon layer 320. A silicide layer is formed on the silicon layer 330 by self-aligning silicide process. Thus, the problem of the surface irregular reflection of the light in photoengraving process can be solved, and the formation of a gate pattern can be performed highly accurately.

公开(公告)号：JPH1116847A

公开(公告)日：1999-01-22

申请号：JP15851097

申请日：1997-06-16

Applicant: UNITED MICROELECTRONICS CORP

Inventor： SHA EIFUN

IPC: H01L21/265

Abstract: PROBLEM TO BE SOLVED: To provide a method for preventing defective structure of crystalline lattice generated at the process of ion implantation in a substrate or annealing. SOLUTION: A maximum angle θ between solid phase epitaxial regrowing ends is selected. A projection width of an ion implantation distance Rp into a substrate, a projected standard deviation ΔRp in the direction of a first axis and a projected standard deviation ΔY in the direction of a second axis are determined. An expression t=Rp+cosθ[ (ΔYsinθ) +(ΔRpcosθ) } ] is solved to obtain a minimum thickness t. After a surface layer 146 having the minimum thickness t has formed on the substrate, ion implantation is performed. A well 142 is formed for controlling the shape of the area of implantation.

公开(公告)号：JPH10275867A

公开(公告)日：1998-10-13

申请号：JP19130097

申请日：1997-07-16

Applicant: UNITED MICROELECTRONICS CORP

Inventor： ON EIMO

IPC: G11C17/00 ,  H01L21/8246 ,  H01L21/84 ,  H01L27/112

Abstract: PROBLEM TO BE SOLVED: To provide a ROM device in which a source/drain region is insulated from a substrate below the source/drain region by the SOI structure and no leak current flows therebetween. SOLUTION: A source/drain region 50 is insulated from a semiconductor substrate 30 below the source/drain region 50 by an SOI structure, to thereby prevent leak current from bowing therebetween. Failures caused by a diode junction between the semiconductor substrate 30 and the source/drain region 50 is prevented, to thereby improve the operating voltage. The source/drain region 50 of a MOSFET memory cell is formed out of intrinsic amorphous silicon instead of heavily-doped polysilicon. The ROM device manufacturing method is thus quite simplified.