公开(公告)号：JPH07200510A

公开(公告)日：1995-08-04

申请号：JP15321194

申请日：1994-07-05

Applicant: TANDEM COMPUTERS INC

Inventor： MIZANUA MOHAMETSUDO RAAMAN ,  FURETSUDO SHII SABAANITSUKU ,  JIEFU EI SUPURAUSU ,  MAATEIN JIRI GUROOSU ,  PIITAA FUU ,  RATSUSERU MAAKU REKUTAA

IPC: G06F15/177 ,  G06F9/445 ,  G06F9/48 ,  G06F11/16 ,  G06F11/20 ,  G06F11/22 ,  G06F12/02 ,  G06F12/08 ,  G06F13/24 ,  G06F13/36 ,  G06F15/16

Abstract: PURPOSE: To connect a processor interface chip and a maintenance/diagnosis chip between two microprocessors of tandem constitution. CONSTITUTION: The processor interface chip 16 is provided with a logic pipeline- processing a microprocessor request between the microprocessors 12, 40 and a main memory 22, a logic prefetching data before the microprocessors issue a reading request, a logic generating a boot from a code within a physical memory without regard to the fixed memory positions of the microprocessors with respect to a boot code and a logic restricting the stream of interruption information through a processor bus between the microprocessors 12, 40 and the processor interface chip 16. The maintenance/diagnosis chip 14 is provided with a function stopping either one of the microprocessors when an error is detected and reading the state and is provided with a secondary cache 30.

公开(公告)号：JPH07170174A

公开(公告)日：1995-07-04

申请号：JP15073694

申请日：1994-07-01

Applicant: TANDEM COMPUTERS INC

Inventor： RATSUSERU ENU MIRO ,  DEYUUKU GAKU RE ,  FURANKU MIKARAUSUKASU ,  SHII JIYON GUREEBENKENPAA ,  KININGU KUWAN

IPC: G06F1/12 ,  G06F1/06 ,  G06F11/16 ,  H03K5/15 ,  H03L7/00

Abstract: PURPOSE: To ensure the proper operation of a system by generating plural frequency clock signals, generating an error signal when incoincidence is detected between the clocks, and re-setting a clock generating means to a prescribed state in response to the error signal. CONSTITUTION: A clock generator system 10 is provided with an error detecting logic, and receives 25 output clock signals from a master clock generating unit 12a and 25 output clocks from a shadow clock generating unit 12b. The error detecting logic compares the output signal of the unit 12a with the corresponding signal of the unit 12b, and outputs an ERROR signal when incoincidence is detected. Next, a reset logic 32 generates a reset signal, and connects a frequency divider 30 of the units 12a and 12b so that they can be reset to the same reset state, re-started, and restored from the error.

公开(公告)号：JPH07168645A

公开(公告)日：1995-07-04

申请号：JP14900294

申请日：1994-06-30

Applicant: TANDEM COMPUTERS INC

Inventor： RINDA WAI ITSUPU ,  KININGU KUWAN

IPC: G06F1/10

Abstract: PURPOSE: To limit clock skew generated in clock signals as much as possible and to distribute the clock signals on an integrated circuit chip by receiving the clock signals by an input terminal and transmitting them to a straight route and a closed loop route. CONSTITUTION: The integrated circuit chip 12a receives the clock signals transmitted by a clock bus 16 by an input pad 20. The input pad 20 is connected through pre-driver circuits 26a and 26b to the respectively two sets of driver circuits 28a and 30a and 28b and 30b. The driver circuit 28 is provided with a pair of drivers parallelly connected to the end part 33 of the straight route 36 formed at the center of the chip 12a. The driver circuit 30 is connected to the closed loop route 34 at points positioned on the opposite side of each other. The closed loop route 34 is formed near the periphery of the chip 12a. The clock input of an I/O device is connected to the closed loop route 34 by branching connection 35 and the clock input of an internal device is connected to the straight route 36 by the branching connection 37.

公开(公告)号：JPH07141286A

公开(公告)日：1995-06-02

申请号：JP14731894

申请日：1994-06-29

Applicant: TANDEM COMPUTERS INC

Inventor： IEI FUON DAN

IPC: G06F13/16 ,  G11C7/10 ,  G11C7/22

Abstract: PURPOSE: To provide a memory interface for an ASIC or non-ASIC circuit for guaranteeing that data holding time is sufficient at all times for a data write operation and ensuring the optimization of performance by not making the data holding time so long. CONSTITUTION: The memory interface 120 on a semiconductor integrated circuit 100 is used for writing data to an external memory 110 by the clocking of write strobe signals and requests that the data are effectively held for little time after the write strobe signals are non-stated. The memory interface 200 allows and inhibits the use of the semiconductor IC by transferring the data to a data bus 140 connected to the external memory 110 by the statement and non-statement of the write strobe signals. The data are stably kept on the data bus 140 while the write strobe signals are stated and allowed to be unstable only after the write strobe signals are non-stated.

公开(公告)号：JPH0773059A

公开(公告)日：1995-03-17

申请号：JP5657794

申请日：1994-03-02

Applicant: TANDEM COMPUTERS INC

Inventor： RICHIYAADO EI BURUBA ,  JIEIMUZU ESU KURETSUKA ,  KAIRAN TABURIYU FUEI JIYUNIA ,  RARII ERU RAMANO ,  NIKIIRU EI MEETA

IPC: G06F11/18 ,  G06F11/16 ,  G06F15/16

Abstract: PURPOSE: To sufficiently and effectively utilize the high-speed throughput of a high-speed processor, in a fault-tolerant computer system. CONSTITUTION: Concerning this fault tolerant type computer system, a multiplex CPU is used for executing the same instruction stream at independent clock cycle timing. The CPU internally executes instructions until its input or output operation requires access to a memory or a device asynchronous with a local CPU clock. Concerning such an input/output operation, each CPU is forced to complete the input/output operation by using the equal number of clock cycles. When the input/output operation is completed, the clocks for the internal processing of the instruction stream are put in order inside each CPU but these clocks are continued while being possible disconnected in real time by drift of an oscillator. The accumulated drift is periodically removed by timer interruption for synchronizing the CPU with each other in real time.

公开(公告)号：JPH0630519B2

公开(公告)日：1994-04-20

申请号：JP24038184

申请日：1984-11-14

Applicant: TANDEM COMPUTERS INC

Inventor： UIRIAMU AARU GUTSUDOMAN

IPC: G06F17/40 ,  G06F11/00 ,  G06F11/07 ,  G06F13/12 ,  G06F13/22 ,  G06F13/42 ,  H04L12/52 ,  H04L12/44

公开(公告)号：JPH0449279B2

公开(公告)日：1992-08-11

申请号：JP24038284

申请日：1984-11-14

Applicant: TANDEM COMPUTERS INC

Inventor： KAARU JEI BEIRII

IPC: H02B1/16 ,  G05F1/00 ,  H05K7/02 ,  H05K9/00

公开(公告)号：JPH03116235A

公开(公告)日：1991-05-17

申请号：JP13242590

申请日：1990-05-22

Applicant: TANDEM COMPUTERS INC

Inventor： ROBAATO ERU JIYAADEIIN ,  SHIYANON JIEI RINCHI ,  FUIRITSUPU AARU MANERA ,  ROBAATO DABURIYUU HOOSUTO

IPC: G06F9/38

Abstract: PURPOSE: To fetch an exact next instruction in a pipe line by comparing a branching prediction bit with a branching condition bit, and testing the error of the prediction. CONSTITUTION: Two cases related with a condition branching instruction are identified according to whether or not the previous instructions are included in a present family, and when a branching condition bit(BCB) is not matched to a branching prediction bit(BPB) from a hierachy PID register 120, branching is a predicted error, and the output of a comparator 124 opens an AND gate 128. Afterwards, an (n) bit hierachy 4 microcode field is transmitted to a decoder (DECA) 139, and a control signal necessary for executing a branching predicting mechanism is generated. Thus, the exact next instruction can be fetched.

公开(公告)号：JPH022207A

公开(公告)日：1990-01-08

申请号：JP28870088

申请日：1988-11-15

Applicant: TANDEM COMPUTERS INC

Inventor： OORANGUZEBU KEI KAAN

IPC: H03K19/0175 ,  H03K19/018 ,  H03K19/082

Abstract: PURPOSE: To attain a driver/receiver integrated circuit of a low cost and a high density by using the same circuit constitutional parts for executing two individual circuit functions. CONSTITUTION: An I/O transceiver (i.e. a receiver/driver) is provided by one composite circuit. A resistor RRR1, transistors(TRs) QQQ1, QQQ2 and a diode DDD1 form a part of both the circuits. Consequently cost reduction can be attained in both of the number of points of a device and the real application area of silicon as compared with a conventional settlement counterplan using two independent circuits.

公开(公告)号：JPH01280843A

公开(公告)日：1989-11-13

申请号：JP30046388

申请日：1988-11-28

Applicant: TANDEM COMPUTERS INC

Inventor： MAATEIN DABURIYUU SANAA ,  SHIIMA CHIYANDORA

IPC: G06F11/30 ,  G06F11/00 ,  G06F11/26 ,  G06F11/28 ,  G06F13/00

Abstract: PURPOSE: To guarantee the correct operation of a state machine by rewriting a slave state machine by an emulator in response to control signals from a master state machine, checking respective assumed states rewritten by the emulator and generating error signals in the case of an erroneous operation. CONSTITUTION: The slave state machine 40 to be rewritten by the emulator receives signals from a state decoder 34 for assuming the states same as the ones assumed by the state machine of a slave control unit 22. The output of the slave state machine 40 is added to a state sequence checker unit similarly to the output of the master state machine 30. A state sequence checker 42 performs checking by a method for deciding whether or not the respective states assumed by the two state machines 30 and 40 are correct, and when they are not correct, the state sequence checker 42 originates the error signals for indicating a problem. Thus, the correct operation of the state machine is guaranteed.