公开(公告)号：KR1020040020532A

公开(公告)日：2004-03-09

申请号：KR1020020052141

申请日：2002-08-30

Applicant: 삼성전자주식회사

Inventor： 오재희 ,  김동우

IPC: H01L21/66

Abstract: PURPOSE: A semiconductor device is provided to prevent generation of particles in a lower electrode by using a line type TEG(Test Electrical Group) pattern. CONSTITUTION: A storage node(24) is arranged to cross the cell gates and spaced apart from cell gates(21). A gate node(21) is connected to the cell gates. A TEG pattern(28) is connected to the storage node. At this time, the TEG pattern(28) has a line shape having constant width. Preferably, the line-width of the TEG pattern(28) is 0.5 micrometer below.

Abstract translation: 目的：提供半导体器件以通过使用线型TEG（测试电气组）图案来防止下电极中的颗粒产生。 构成：存储节点（24）布置成跨越单元栅极并与单元栅极（21）间隔开。 门节点（21）连接到单元门。 TEG模式（28）连接到存储节点。 此时，TEG图案（28）具有恒定宽度的线状。 优选地，TEG图案（28）的线宽度在0.5微米以下。

公开(公告)号：KR1020020042309A

公开(公告)日：2002-06-05

申请号：KR1020000072131

申请日：2000-11-30

Applicant: 삼성전자주식회사

Inventor： 오재희

IPC: H01L21/24

Abstract: PURPOSE: A fabrication method of a semiconductor memory device is provided to simplify manufacturing processes by selectively forming a transition metal silicide layer using a hard density plasma insulating layer. CONSTITUTION: Silicide prevention layers made of a buffer insulating layer(64) and a silicon nitride(66) is deposited on a substrate(50) defined with DRAM cell region(B1) and a logic cell region(B2) respectively having gate electrodes(g), source regions(60a,62a), and drain regions(60b,62b). The first transition metal silicide layers(70a,70b) are selectively formed on the gate electrodes(g), source and drain regions(60a,60b,62a,62b) in the logic cell region(B2). An etch stopper(72) is deposited on the resultant structure and a hard density plasma insulating layer(74) is then formed to fill the gap between the gate electrodes(g). The hard density plasma insulating layer(74), the etch stopper(72) and the silicide prevention layers(64,66) are etched to expose the gate electrodes(g) in the DRAM cell region(B1). Then, the second transition metal silicide layer(78) is formed on the gate electrodes(g) in the exposed DRAM cell region(B1).

Abstract translation: 目的：提供半导体存储器件的制造方法，以通过使用硬密度等离子体绝缘层选择性地形成过渡金属硅化物层来简化制造工艺。 构成：由缓冲绝缘层（64）和氮化硅（66）制成的防硅层被沉积在由DRAM单元区域（B1）和逻辑单元区域（B2）限定的基板（50）上，该区域分别具有栅电极 g），源极区（60a，62a）和漏极区（60b，62b）。 第一过渡金属硅化物层（70a，70b）选择性地形成在逻辑单元区域（B2）中的栅极（g），源极和漏极区（60a，60b，62a，62b）上。 在所得结构上沉积蚀刻停止器（72），然后形成硬密度等离子体绝缘层（74）以填充栅电极（g）之间的间隙。 蚀刻硬密度等离子体绝缘层（74），蚀刻停止层（72）和硅化物防止层（64,66）以暴露DRAM单元区域（B1）中的栅电极（g）。 然后，在暴露的DRAM单元区域（B1）中的栅电极（g）上形成第二过渡金属硅化物层（78）。

公开(公告)号：KR1020020042308A

公开(公告)日：2002-06-05

申请号：KR1020000072130

申请日：2000-11-30

Applicant: 삼성전자주식회사

Inventor： 문창록 ,  김동우 ,  박종우 ,  오재희

IPC: H01L29/78

Abstract: PURPOSE: A fabrication method of semiconductor device having a double gate poly-structure capable of forming an SAC(Self-Aligned Contact) and a gate structure thereof are provided to prevent a characteristic attenuation of a PMOS(P-type Metal Oxide Semiconductor) transistor due to boron permeance by forming a gate using a compact gate insulating layer and a DCS-Wsix layer having poor fluorine ions. CONSTITUTION: A gate stack having a first insulating layer(110) made of a NOX(Nitrogen-rich Oxynitride), a second insulating layer(120), a gate conductive layer(170) made of a DCS-Wsix layer having poor fluorine ions, and a third gate insulating layer(160) is formed by stacking the layers(110,120,170,160). At this time, P-type ions and N-type ions are selectively implanted to the second insulating layer(120) for forming a PMOS transistor and an NMOS transistor. Transistor gates(190,200,210) are formed by etching the gate stack and spacers(140) made of a silicon nitride are then formed on both sidewalls of the transistor gates(190,200,210). After forming and patterning an oxide(180), a contact hole is formed by etching the oxide(180) using a self-aligned method.

Abstract translation: 目的：提供具有能够形成SAC（自对准接触）的双栅多晶硅结构及其栅极结构的半导体器件的制造方法，以防止PMOS（P型金属氧化物半导体）晶体管的特性衰减 由于通过使用紧凑的栅极绝缘层形成栅极的硼渗透和具有差的氟离子的DCS-Wsix层。 构成：具有由NOX（富氮氧化物）构成的第一绝缘层（110），第二绝缘层（120），由具有差的氟离子的DCS-Wsix层制成的栅极导电层（170）的栅堆叠 ，并且通过堆叠层（110,120,170,160）形成第三栅极绝缘层（160）。 此时，P型离子和N型离子选择性地注入用于形成PMOS晶体管和NMOS晶体管的第二绝缘层（120）。 通过蚀刻栅叠层形成晶体管栅极（190,200,210），然后在晶体管栅极（190,200,210）的两个侧壁上形成由氮化硅制成的间隔物（140）。 在形成和图案化氧化物（180）之后，通过使用自对准方法蚀刻氧化物（180）形成接触孔。

公开(公告)号：KR102059865B1

公开(公告)日：2020-02-12

申请号：KR1020130093200

申请日：2013-08-06

Applicant: 삼성전자주식회사

Inventor： 유경창 ,  정홍식 ,  강대환 ,  오재희 ,  유지형

IPC: G11C13/00

公开(公告)号：KR101598378B1

公开(公告)日：2016-02-29

申请号：KR1020090018486

申请日：2009-03-04

Applicant: 삼성전자주식회사

Inventor： 김정인 ,  오재희 ,  김현호 ,  정지현

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L45/16 ,  H01L27/1021 ,  H01L27/24

Abstract: 메모리소자의형성방법을제공한다. 기판상에하부전극을형성하고, 상기하부전극상에제 1 식각방지층및 제 2 식각방지층을적층하고, 상기식각방지층상에절연층을형성하고, 상기절연층과상기식각방지층을패터닝하여상기하부전극을노출시키는리세스영역을형성하고, 상기리세스영역에가변저항물질층을형성하고, 그리고상기가변저항물질층상에상부전극을형성하는것을포함하고, 상기제 1 식각방지층은상기제 2 식각방지층과식각선택도가있다.

公开(公告)号：KR101535653B1

公开(公告)日：2015-07-10

申请号：KR1020090010222

申请日：2009-02-09

Applicant: 삼성전자주식회사

Inventor： 은성호 ,  오재희

IPC: H01L21/8247 ,  H01L27/115 ,  H01L21/768

CPC classification number: H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/143 ,  H01L45/144 ,  H01L45/16

Abstract: 본발명은상변화메모리소자의제조방법에관한것으로, 상변화물질막이포함된기판을제공하고, 상기기판상에상기상변화물질막을덮는절연막을형성하고, 상기절연막을패터닝하여상기상변화물질막을노출시키는콘택홀을형성하고, 상기콘택홀의일부를채우는상기상부전극을형성하고, 상기콘택홀의나머지일부를채우며상기상부전극과자기정렬된상기비트라인을형성하는것을특징으로한다.

公开(公告)号：KR1020130005878A

公开(公告)日：2013-01-16

申请号：KR1020110067535

申请日：2011-07-07

Applicant: 삼성전자주식회사

Inventor： 박종현 ,  오재희 ,  박규술

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L27/1021 ,  H01L27/101 ,  H01L27/11507 ,  H01L27/224 ,  H01L27/2409 ,  H01L29/8613 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/146 ,  H01L29/45

Abstract: PURPOSE: A low resistive semiconductor device is provided to improve an operation property by maximizing a contact surface of a bottom electrode, an ohmic layer, and a pn junction diode to minimize contact resistance. CONSTITUTION: A first interlayer dielectric layer(107) with a cell contact hole(111) is formed on a word line(102). A pn junction diode(113) is located in the cell contact hole. An ohmic layer(115) to reduce ohmic contact resistance with a bottom electrode(119) is formed on the upper side of the pn junction diode. A storage device(121) is located on the upper side of the bottom electrode. A top electrode(123) and a bit line contact plug(127) are located on the upper side of the storage device.

Abstract translation: 目的：提供一种低电阻半导体器件，以通过使底部电极，欧姆层和pn结二极管的接触表面最大化来改善操作性能，以使接触电阻最小化。 构成：在字线（102）上形成具有单元接触孔（111）的第一层间介质层（107）。 pn结二极管（113）位于电池接触孔中。 在pn结二极管的上侧形成用于降低与底部电极（119）的欧姆接触电阻的欧姆层（115）。 存储装置（121）位于底部电极的上侧。 顶部电极（123）和位线接触插头（127）位于存储装置的上侧。

公开(公告)号：KR1020120104040A

公开(公告)日：2012-09-20

申请号：KR1020110022107

申请日：2011-03-11

Applicant: 삼성전자주식회사

Inventor： 박규술 ,  오재희 ,  주흥진

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L45/06 ,  H01L27/2409 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1675 ,  H01L45/143

Abstract: PURPOSE: A phase change memory device and a manufacturing method thereof are provided to have an etch stop layer including a metal oxide layer which an etch selection ratio is higher than the ratio of a metal nitride layer of a lower portion electrode, thereby minimizing damage of the lower portion electrode, when a knoll structure is formed. CONSTITUTION: A mold oxide layer is formed on a substrate. A lower portion electrode(30) is formed on the mold oxide layer. The lower portion electrode is connected to the substrate. A knoll structure(40) covers a part of the lower portion electrode. The knoll structure includes an etch stop layer(42) and a knoll insulation layer. A phase change layer covers the rest of the lower portion electrode exposed from the knoll structure. The etch stop layer includes a material which is a high etch selection ratio for the lower portion electrode.

Abstract translation: 目的：提供一种相变存储器件及其制造方法，以具有包括金属氧化物层的蚀刻停止层，其蚀刻选择比高于下部电极的金属氮化物层的比例，从而最小化损伤 下部电极，当形成结构时。 构成：在基板上形成模具氧化物层。 在模具氧化物层上形成下部电极（30）。 下部电极与基板连接。 榫头结构（40）覆盖下部电极的一部分。 结构结构包括蚀刻停止层（42）和绝缘层。 相变层覆盖从knoll结构暴露的下部电极的其余部分。 蚀刻停止层包括对于下部电极是高蚀刻选择比的材料。

公开(公告)号：KR1020120040516A

公开(公告)日：2012-04-27

申请号：KR1020100101982

申请日：2010-10-19

Applicant: 삼성전자주식회사

Inventor： 김진영 ,  송기환 ,  오재희 ,  정지현

IPC: G11C7/12 ,  G11C7/18 ,  G11C13/00 ,  H01L27/24

CPC classification number: H01L27/2409 ,  G11C7/12 ,  G11C7/18 ,  G11C13/0004 ,  G11C2213/72 ,  G11C2213/79 ,  H01L27/2436 ,  G11C16/30 ,  G11C13/02 ,  G11C16/08 ,  G11C16/24

Abstract: PURPOSE: A memory device, a manufacturing method thereof, and a memory system including the same are provided to reduce discharge time by discharging a bit line voltage using a diode. CONSTITUTION: A memory device includes a plurality of sub cell arrays(21-1) and a switch. A plurality of sub cell arrays include a plurality of memory cells(23-1 to 23-n), a discharge line and a plurality of diodes. The plurality of memory cells are arranged in an intersection between a plurality of local bit lines and a plurality of word lines. A plurality of diodes(24) are connected between the plurality of local bit lines and the discharge line. A switch connects the discharge lien and the ground in response to a discharge enable signal.

Abstract translation: 目的：提供一种存储器件及其制造方法和包括该存储器件的存储器系统，以通过使用二极管放电位线电压来减少放电时间。 构成：存储器件包括多个子单元阵列（21-1）和开关。 多个子单元阵列包括多个存储单元（23-1至23-n），放电线和多个二极管。 多个存储单元布置在多个局部位线和多个字线之间的交叉点中。 多个二极管（24）连接在多个局部位线与放电线之间。 开关响应于放电使能信号连接放电留置和接地。

公开(公告)号：KR1020110135769A

公开(公告)日：2011-12-19

申请号：KR1020100055689

申请日：2010-06-11

Applicant: 삼성전자주식회사

Inventor： 김성원 ,  박재현 ,  오재희

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: G11C5/063 ,  G11C8/14 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0028 ,  H01L27/105 ,  H01L27/2436 ,  H01L27/2409 ,  H01L45/04 ,  H01L45/06 ,  H01L45/143 ,  H01L45/144

Abstract: PURPOSE: A non-volatile memory device is provided to improve reliability by largely forming the pitch of a circuit word line pattern than the pitch of a cell word line pattern which is adjacent. CONSTITUTION: A plurality of variable resistor elements is formed in the top of a substrate. A plurality of bit lines(BL) is extended to a first direction on a plurality of variable resistor elements and is separately formed to a first pitch(P1). A plurality of cell word lines is extended to a second direction on a plurality of bit lines and is separately formed to a second pitch(P2). A plurality of circuit word lines is extended to the first direction on a plurality of bit lines is separately formed to a third pitch(P3). The third pitch of a plurality of circuit word lines is bigger than the first pitch of a plurality of bit lines.

Abstract translation: 目的：提供一种非易失性存储器件，通过大大地形成电路字线图案的间距，而不是相邻的单元格字线图形的间距来提高可靠性。 构成：在基板的顶部形成多个可变电阻元件。 多个位线（BL）在多个可变电阻器元件上延伸到第一方向，并且分开地形成为第一间距（P1）。 多个单元字线在多个位线上延伸到第二方向，并且分开地形成为第二间距（P2）。 多个电路字线在多个位线上向第一方向延伸，分别形成为第三间距（P3）。 多个电路字线的第三间距大于多个位线的第一间距。