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公开(公告)号：DE69226766D1
公开(公告)日：1998-10-01
申请号：DE69226766
申请日：1992-06-22
Applicant: IBM
Inventor： BASSO CLAUDE , VERPLANKEN FABRICE , CALVIGNAC JEAN
IPC: G06F13/00 , H04L7/00 , H04L12/433 , H04L12/64 , H04L12/42
Abstract: A hub featuring several ports for attachment of stations to a LAN comprises concentration logic (14) for the handling of multiplexed incoming and outgoing Token-Ring and isochronous flows from and to the stations. The concentration logic comprises a clock recovery logic (42) from incoming Token-Ring packet data stream (40), for regeneration of Differential Manchester encoded data on output (400), and recovering of Token-Ring clock (401). A cycle framing generator (43) receives a 125 us synchronization clock (local or remote) from the hub backplane (402), and the Token-Ring clock (401), and generates control signals (403) to each of the 10 ports. Each port is made up of a port transmit interface (44), and a port receive interface (45). Data from a station hooked to the hub is input (404) to port receive interface (45). Token-Ring packet Differential Manchester encoded data are output (406) on to the next active port, and specifically to its port transmit interface, along with a recovered strobe clock (405), while ISO data are output (407) to a switch (46). The switch receives a hub local clock (412), which otherwise distributes on the whole concentration logic. isochronous traffic interchange with the hub backplane is ensured thru leads 410 and 411; inbetween ports or between ports and the hub is ensured thru leads 407 and 409 replicated for each port. Data to the station hooked to the hub is output (408) from port transmit interface (44). Differential Manchester encoded data are received (400) along with Token-Ring clock (401). Control signals are input (403). Isochronous data are received (409). Token-Ring packet Differential Manchester encoded data are finally output from the concentration logic (41).
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公开(公告)号：DE69017198D1
公开(公告)日：1995-03-30
申请号：DE69017198
申请日：1990-05-15
Applicant: IBM
Inventor： CALVIGNAC JEAN , SAINT GEORGES ERIC , ORSATTI DANIEL , TOUBOL GILLES , VERPLANKEN FABRICE , NICOLAS FRANCOIS
Abstract: The hybrid packet and circuit switching system allows to merge the packet and circuit traffics from user interface modules 2-1 to 2-N on TDM bus 4-1 to 4N and to transfer packet information from one module to another module or exchange circuit information between modules. The circuit exchange or packet transfers are performed synchronously on the TDM busses in bursts of period T, with each burst comprising a fixed number of bytes. The bursts are switched by switch 1. There is a routing indication which is common to the packet and circuit bursts for controlling the switching of the bursts by the switch 1, which is performed by piggy backing the target module address for the circuit bursts as well as for the packet burst with the data bursts. The marking tables which are needed for the circuit burst allocation are located in the user interface modules.
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公开(公告)号：DE3850881T2
公开(公告)日：1995-03-09
申请号：DE3850881
申请日：1988-10-28
Applicant: IBM
Inventor： CALVIGNAC JEAN , LIPS JEAN-PIERRE , MILLET JEAN-MARC , MUNIER JEAN-MARIE , NAUDIN BERNARD
IPC: G06F15/16 , G06F13/38 , G06F13/42 , G06F15/167 , G06F15/177
Abstract: The memory comprises a linear space and a buffered space, each page of the buffered space is divided in a number m+1 of buffers of equal capacity, with m buffers devoted to the storage of data and one control buffer divided into m control blocks. There is a fixed relationship between one buffer control block and one data buffer. The control blocks are devoted to the storage of buffer and message chaining information. The linear space comprises queue control blocks, with one queue control block per user. The messages are received by memory interface 22 from the source users and then are enqueued in link inbound queues (LIQ) which are dynamically built by taking buffers from the buffered space, chaining the buffers by writing buffer and message chaining information in the corresponding buffer control blocks and writing the queue head and queue tail addresses in the user queue control block. A centralized control means is designed to process enqueue, dequeue and release orders upon requests from a user selected by an arbitrating means. When a link inbound queue becomes not empty, the memory interface 22 sends a dequeue order request to the centralized control means, said request identifying the corresponding user queue control block. The message address is provided in response thereto with the identification of the queue control block of the destination user. Then, the memory interface 22 sends an enqueue request to the centralized control means, said request identifying the address of the message to be enqueued and the queue control block of the destination user. The processing of this enqueue request by the centralized control means causes the messages to be enqueued in an outbound queue from which it is transferred to the destination user, by memory interface 22.
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44.发明专利
公开(公告)号：CA2018068C
公开(公告)日：1994-09-06
申请号：CA2018068
申请日：1990-06-01
Applicant: IBM
Inventor： CALVIGNAC JEAN , FERAUD JACQUES , LIPS JEAN-PIERRE , NAUDIN BERNARD , SAINT-GEORGES ERIC
Abstract: The subject distribution mechanism is used in a communication system comprising a plurality of interfaces, (10, 11 and 12) with each interface connected to at least one user and able to receive and transmit information to said user(s) through information carrying means. It allows communications to be established between users selected by a central control unit (7) in a programmable way. The distribution mechanism comprises: in each interface, scheduling means responsive to a common timing signal having a period T, to divide the period into n slot periods having a slot number, n being the number of users connected to that interface to which the maximum number of users are connected, a configuration table (18) comprising n locations, each location assigned to a slot period, the central control unit writing in each location communication control information, said table being addressed by the slot numbers generated by the scheduling means to read and make available, the communication control information, distribution buffer means (20) comprising at least a first and a second part, each part having n addressable locations, addressed by means of addressing means responsive to the communication control information provided by the configuration table during each slot period to cause each interface involved in the to be established communications during that slot period, to write the information to be transmitted in one part of the distribution buffer and the information to be received by the interface to be read from the other part of the distribution buffer at addresses derived from the communication control information and the slot number generated by the scheduling means.
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公开(公告)号：DE3850881D1
公开(公告)日：1994-09-01
申请号：DE3850881
申请日：1988-10-28
Applicant: IBM
Inventor： CALVIGNAC JEAN , LIPS JEAN-PIERRE , MILLET JEAN-MARC , MUNIER JEAN-MARIE , NAUDIN BERNARD
IPC: G06F15/16 , G06F13/38 , G06F13/42 , G06F15/167 , G06F15/177
Abstract: The memory comprises a linear space and a buffered space, each page of the buffered space is divided in a number m+1 of buffers of equal capacity, with m buffers devoted to the storage of data and one control buffer divided into m control blocks. There is a fixed relationship between one buffer control block and one data buffer. The control blocks are devoted to the storage of buffer and message chaining information. The linear space comprises queue control blocks, with one queue control block per user. The messages are received by memory interface 22 from the source users and then are enqueued in link inbound queues (LIQ) which are dynamically built by taking buffers from the buffered space, chaining the buffers by writing buffer and message chaining information in the corresponding buffer control blocks and writing the queue head and queue tail addresses in the user queue control block. A centralized control means is designed to process enqueue, dequeue and release orders upon requests from a user selected by an arbitrating means. When a link inbound queue becomes not empty, the memory interface 22 sends a dequeue order request to the centralized control means, said request identifying the corresponding user queue control block. The message address is provided in response thereto with the identification of the queue control block of the destination user. Then, the memory interface 22 sends an enqueue request to the centralized control means, said request identifying the address of the message to be enqueued and the queue control block of the destination user. The processing of this enqueue request by the centralized control means causes the messages to be enqueued in an outbound queue from which it is transferred to the destination user, by memory interface 22.
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Patent Agency Ranking
公开(公告)号：DE3786404T2
公开(公告)日：1994-01-20
申请号：DE3786404
申请日：1987-11-27
Applicant: IBM
Inventor： CALVIGNAC JEAN , LENOIR RAYMOND , DAUPHIN MICHEL , PICARD JEAN-LOUIS
Abstract: A data handling system wherein data are arranged into frames including an information data section and a frame check sequence (FCS) section, and wherein a stamp section has to be appended/deleted from said frame. The stamp appending is operated without any FCS updating being required by appending to each stamp, a so called precomputed and stored anti-stamp.
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公开(公告)号：DE3786404D1
公开(公告)日：1993-08-05
申请号：DE3786404
申请日：1987-11-27
Applicant: IBM
Inventor： CALVIGNAC JEAN , LENOIR RAYMOND , DAUPHIN MICHEL , PICARD JEAN-LOUIS
Abstract: The system includes a device for generating an antistamp section made to neutralise the contribution of the stamp section to FCS, a device for appending anti-stamp section to the stamp section so that a tag is generated and a device for appending tag to data section. The FCS is the remainder of the division of a polynomial representation of data section by a predetermined generating polynomial G(X). A stamp storage is used for storing a so called stamp representing the TDM slot reference corresponding to each HDLC frame. An anti-stamp storage serves for storing predetermined stamp dependant anti-stamp data.
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48.发明专利
公开(公告)号：CA1320590C
公开(公告)日：1993-07-20
申请号：CA607308
申请日：1989-08-02
Applicant: IBM
Inventor： CALVIGNAC JEAN , LIPS JEAN-PIERRE , MILLET JEAN-MARC , MUNIER JEAN-MARIE , NAUDIN BERNARD
IPC: G06F15/16 , G06F13/38 , G06F13/42 , G06F15/167 , G06F15/177
Abstract: MECHANISM FOR TRANSFERRING MESSAGES BETWEEN SOURCE AND DESTINATION USERS THROUGH A SHAPED MEMORY The present invention relates to a mechanism for managing a memory shared between a number of users, so that the users may exchange messages through the memory, in a performant way. The memory comprises a linear space and a buffered space, each page of the buffered space is divided in a number m+1 of buffers of equal capacity, with m buffers devoted to the storage of data and one control buffer divided into m control blocks. There is a fixed relationship between one buffer control block and one data buffer. The control blocks are devoted to the storage of buffer and message chaining information. The linear space comprises queue control blocks, with one queue control block per user. Messages are received by a memory interface from source users and then are enqueued in link inbound queues which are dynamically built by taking buffers from the buffered space, chaining the buffers by writing buffer and message chaining information in the corresponding buffer control blocks and writing the queue head and queue tail addresses in the user queue control block. A centralized control means is designed to process, enqueue, dequeue and release orders upon requests from a user selected by an arbitrating means. When a link inbound queue becomes not empty, the memory interface sends a dequeue order request to the centralized control means, said request identifying the corresponding user FR9-88-009 queue control block. The message address is provided in response thereto with the identification of the queue control block of the destination user. Then, the memory interface sends an enqueue request to the centralized control means, said request identifying the address of the message to be enqueued and the queue control block of the destination user. The processing of this enqueue request by the centralized control means causes the messages to be enqueued in an outbound queue from which it is transferred to the destination user, by the memory interface. FR9-88-009
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公开(公告)号：DE3785211D1
公开(公告)日：1993-05-06
申请号：DE3785211
申请日：1987-10-30
Applicant: IBM
Inventor： CALVIGNAC JEAN , DAUPHIN MICHEL , LENOIR RAYMOND , PICARD JEAN-LOUIS
Abstract: The entire frame (Mr(x)) as received is serialised under clock control at bit rate which also governs serialisation of the new header (Ht(x)) extracted from a buffer register. The serialisers' outputs are gated by a HEADER GATE signal and its inverse. An Exclusive-OR operation is applied to the modified and previous polynomial headers in order to generate the difference polynomial (D(x)) on which a differential frame check polynomial sequence (dFCS) is computed for modulo-2 addn. to the original frame check sequence. The sum iss inserted in the SDLC frame at the proper location.
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50.发明专利
公开(公告)号：CA1313412C
公开(公告)日：1993-02-02
申请号：CA597345
申请日：1989-04-20
Applicant: IBM
Inventor： CALVIGNAC JEAN , FERAUD JACQUES , NAUDIN BERNARD , PIN CLAUDE , SAINT-GEORGES ERIC
Abstract: FR 9 88 005 PARALLEL PROCESSING METHOD AND DEVICE FOR RECEIVING AND TRANSMITTING HDLC SDLC BIT STREAMS This invention relates to a parallel processing method and device for receiving and transmitting HDLC (high level data link control) frames, which improves the performance of a data communication apparatus in a significant way. The bit streams transporting the frames, received from lines 6 are inputted in to register 12, in such a way that n bits are processed during a time interval T. Parallel processor 10 counts the consecutive bits at 1 from the n bits received in interval T and from the bits received in the previous interval T-1, to determine when this number is found equal to 5 which bits have to be deleted, and when this number is found equal to 6 whether a flag is received. As a result it rassembles N-bits characters, with N>n, in register 16. The frame characters to be sent on lines 6 are stored into register 28, and processed in parallel in a time interval T by processor 10 which inserts 0 after five consecutive 1 as a function of the value of the N-bits and as a function of the bit of the previous character, to store into register 32, the bits which are sent on lines 6. (Figure 2)
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