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    SOI DEVICE WITH REDUCED JUNCTION CAPACITANCE.
    41.
    发明专利
    SOI DEVICE WITH REDUCED JUNCTION CAPACITANCE. 未知

    公开(公告)号：MY127799A

    公开(公告)日：2006-12-29

    申请号：MYPI20021672

    申请日：2002-05-09

    Applicant: IBM

    Inventor： FURUKAWA TOSHIHARU

    IPC: H01L21/336 ,  H01L27/01 ,  H01L29/786

    Abstract: AN SOI FET COMPRISING A SILICON SUBSTRATE (300, 400) HAVING SILICON LAYER (310, 410) ON TOP OF A BURIED OXIDE LAYER (305, 405) HAVING DOPED REGIONS AND AN UNDOPED REGION IS DISCLOSED. THE DOPED REGION HAS A DIELECTRIC CONSTANT DIFFERENT FROM THE DIELECTRIC CONSTANT OF THE DOPED REGIONS. A BODY (370, 470) ALSO IN THE SILICON LAYER SEPARATES THE SOURCE/DRAINS (365, 465) IN THE SILICON LAYER. THE SOURCE/DRAINS ARE ALIGNED OVER THE DOPED REGIONS AND THE BODY IS ALIGNED OVER THE UNDOPED REGION. A GATE DIELECTRIC (325, 425) IS ON TOP OF THE BODY AND A GATE CONDUCTOR (330, 430) IS ON TOP OF THE GATE DIELECTRIC. (FIG. 4)

    METHOD FOR FORMING A HORIZONTAL SURFACE SPACER AND DEVICES FORMED THEREBY
    43.
    发明专利
    METHOD FOR FORMING A HORIZONTAL SURFACE SPACER AND DEVICES FORMED THEREBY 未知

    公开(公告)号：MY117065A

    公开(公告)日：2004-04-30

    申请号：MYPI9904306

    申请日：1999-10-06

    Applicant: IBM

    Inventor： FURUKAWA TOSHIHARU ,  HAKEY MARK C ,  HOLMES STEVEN J ,  HORAK DAVID V ,  RABIDOUX PAUL A

    IPC: H01L21/22 ,  H01L21/033 ,  H01L21/308 ,  H01L21/336 ,  H01L21/425 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8234 ,  H01L29/78

    Abstract: THE PRESENT INVENTION PROVIDES A METHOD FOR FORMING SELF-ALIGNED SPACERS (502) ON THE HORIZONTAL SURFACES WHILE REMOVING SPACER MATERIAL FROM THE VERTICAL SURFACES. THE PREFERRED METHOD USES A RESIST(302) THAT CAN BE MADE INSOLUBLE TO DEVELOPER BY THE USE OF AN IMPLANT. BY CONFORMALLY DEPOSITING THE RESIST OVER A SUBSTRATE (202) HAVING BOTH VERTICAL AND HORIZONTAL SURFACES, IMPLANTING THE RESIST, AND DEVELOPING THE RESIST, THE RESIST IS REMOVED FROM THE VERTICAL SURFACES WHILE REMAINING ON THE HORIZONTAL SURFACES. THUS, A SELF-ALIGNED SPACER IS FORMED ON THE HORIZONTAL SURFACES WHILE THE SPACER MATERIAL IS REMOVED FROM THE VERTICAL SURFACES. THIS HORIZONTAL-SURFACE SPACER CAN THEN BE USED IN FURTHER FABRICATION. THE PREFERRED METHOD CAN BEUSED IN MANY DIFFERENT PROCESSES WHERE THERE IS EXISTS A NEED TO DIFFERENTIALLY PROCESS THE VERTICAL AND HORIZONTAL SURFACES OF A SUBSTRATE.FIG. 1

    Method and equipment for cleaning semiconductor substrate in immersion lithography system
    45.
    发明专利
    Method and equipment for cleaning semiconductor substrate in immersion lithography system 有权
    用于在浸没层析系统中清洁半导体衬底的方法和设备

    公开(公告)号：JP2006148093A

    公开(公告)日：2006-06-08

    申请号：JP2005319160

    申请日：2005-11-02

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： HOLMES STEVEN J ,  MARK C HEIKY ,  FURUKAWA TOSHIHARU ,  DAVID V HOLLACK

    IPC: H01L21/027 ,  G03F7/20

    CPC classification number: G03F7/70341 ,  G03F7/70925

    Abstract: PROBLEM TO BE SOLVED: To remove smearing residue in an immersion lithography system. SOLUTION: The equipment for cleaning a semiconductor substrate comprises a chamber having an upper portion, a sidewall and a bottom opening where the upper portion is transparent to light of selected wavelength, an inlet and an outlet provided in the sidewall of the chamber, a plate extending outward from the bottom edge of the chamber, a set of concentric grooves formed in the bottom face of the plate and centering on the chamber, a means for applying vacuum to first and fourth grooves closest to the bottom opening of the chamber in the set of grooves, a means for supplying inert gas or vapor mixture of inert gas and solvent to a second groove between the first and fourth grooves and a fifth groove on the outside of the fourth groove in the set of grooves, and a means for supplying cleaning fluid to a third groove between the second and fourth grooves in the set of grooves. COPYRIGHT: (C)2006,JPO&NCIPI

    Abstract translation: 要解决的问题：去除浸没式光刻系统中的污渍残留物。 解决方案：用于清洁半导体衬底的设备包括具有上部，侧壁和底部开口的室，其中上部对于所选波长的光是透明的，入口和出口设置在室的侧壁中 ，从所述室的底部边缘向外延伸的板，形成在所述板的底面中并且以所述室为中心的一组同心槽，用于对最靠近所述室的底部开口的第一和第四凹槽施加真空的装置 在一组凹槽中，用于将惰性气体或惰性气体和溶剂的惰性气体或蒸汽混合物供应到第一和第四凹槽之间的第二凹槽和该组凹槽中的第四凹槽的外侧上的第五凹槽的装置， 用于将清洁流体供应到所述一组凹槽中的第二和第四凹槽之间的第三凹槽。 版权所有（C）2006，JPO＆NCIPI

    TRENCH STORAGE DRAM CELL CONTAINING STEP TRAVEL ELEMENT AND ITS FORMATION METHOD
    46.
    发明专利
    TRENCH STORAGE DRAM CELL CONTAINING STEP TRAVEL ELEMENT AND ITS FORMATION METHOD 失效

    公开(公告)号：JPH11289069A

    公开(公告)日：1999-10-19

    申请号：JP1527799

    申请日：1999-01-25

    Applicant: IBM

    Inventor： HORAK DAVID VACLAV ,  FURUKAWA TOSHIHARU ,  HOLMES STEVEN JOHN ,  HAKEY MARK CHARLES ,  MA WILLIAM HSIOH-LIEN ,  MANDELMAN JACK ALLAN

    IPC: H01L21/76 ,  H01L21/8242 ,  H01L27/108

    Abstract: PROBLEM TO BE SOLVED: To integrate a step move element adjacent to a deep trench capacitor by arranging an FET on one portion of the deep trench capacitor in a substrate, and providing an insulation region with a larger depth than the FET while surrounding the FET. SOLUTION: An FET is arranged on one portion of a deep trench capacitor 13 in a substrate, a travel element gate 17 is arranged on one portion of the deep trench capacitor 13 in the FET, and an n+ diffusion region 23 being separated from the travel element gate 17 by the insulation layer is formed adjacent to the side part of the travel element gate 17. Also, an isolation region 15 being insulated from the travel element gate 17 of the FET is arranged on one portion of the deep trench capacitor that is not covered with the FET, surrounds the FET and is located in the substrate, thus forming a larger depth than the FET and hence integrating the step travel element adjacent to the deep trench capacitor 13.

    Memory structure and memory structure activation method
    48.
    发明专利
    Memory structure and memory structure activation method 审中-公开
    记忆结构和记忆结构激活方法

    公开(公告)号：JP2007158332A

    公开(公告)日：2007-06-21

    申请号：JP2006322502

    申请日：2006-11-29

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： DAVID VACLAV HORAK ,  KOBURGER CHARLES W III ,  HAKEY MARK CHARLES ,  HOLMES STEVEN J ,  FURUKAWA TOSHIHARU

    IPC: H01L27/10

    CPC classification number: G11C13/025 ,  B82Y10/00 ,  H01L51/0048 ,  H01L51/0512

    Abstract: PROBLEM TO BE SOLVED: To provide a memory cell structure without gate leak current, and an activation method thereof. SOLUTION: The structure includes (a) a substrate, (b) first and second electrode regions 610, 1120 on the substrate, and (c) a third electrode region 1110 arranged between the first electrode region and the second electrode region. When a first write voltage potential is applied between the first electrode and the third electrode region, in response thereto, the third electrode region changes the shape of its own and then, when a predetermined read voltage potential is applied between the first electrode region and the third electrode region, in response thereto, a sense current flows between the first electrode region and the third electrode region. Further, when a second write voltage potential is applied between the second electrode region and the third electrode region, in response thereto, no sense current flows between the first electrode region and the third electrode region. COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：提供没有栅极泄漏电流的存储单元结构及其激活方法。 解决方案：该结构包括（a）基板，（b）基板上的第一和第二电极区域610,1120，以及（c）布置在第一电极区域和第二电极区域之间的第三电极区域1110。 当在第一电极和第三电极区域之间施加第一写入电压电位时，响应于此，第三电极区域改变其本身的形状，然后当在第一电极区域和第二电极区域之间施加预定的读取电压电位时， 响应于此，感测电流在第一电极区域和第三电极区域之间流动。 此外，当在第二电极区域和第三电极区域之间施加第二写入电压电位时，响应于此，第一电极区域和第三电极区域之间没有感测电流流动。 版权所有（C）2007，JPO＆INPIT

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