公开(公告)号：JPH11163297A

公开(公告)日：1999-06-18

申请号：JP27008198

申请日：1998-09-24

Applicant: SIEMENS AG ,  IBM

Inventor： MUELLER GERHARD ,  KIRIHATA TOSHIAKI

IPC: G11C11/403 ,  G11C7/06 ,  G11C11/409 ,  G11C11/4091 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To eliminate remarkable bypass arrangement of a bit line which largely operates on the whole size of a chip, by arranging a master data line switch in a sense amplifier area and occupying spaces at every row corresponding to one driver. SOLUTION: A first part 222a of a driver distributed in a sense amplifier bank is arranged in a stitch area or an idle space formed against a local word line 228. A second part 222b is arranged in a sense amplifier area 224. A master data line switch 220 is provided for an area 226 between segmented parts of a PSET driver or an NSET driver in the sense amplifier area 224. A remarkable bypass arrangement of a bit line which largely operates on the whole size of a chip can be eliminated and space efficiency can be improved.

公开(公告)号：JPH11163296A

公开(公告)日：1999-06-18

申请号：JP27007998

申请日：1998-09-24

Applicant: SIEMENS AG ,  IBM

Inventor： MUELLER GERHARD ,  KIRIHATA TOSHIAKI

IPC: G11C11/401 ,  G11C5/02 ,  G11C7/18 ,  G11C11/409 ,  G11C11/4097 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To reduce number of contact points of a sense amplifier bank, by arranging diffusion area between complementary bit lines, extending diffusion areas in a crossing direction against the direction of a column, and sharing the diffusion areas by means of the other drivers. SOLUTION: A level M0 is provided on an active area AA, complementary bit lines 120 are provided for the level M0 and they are arranged on a first diffusion area 154. Then, a second diffusion area 156 is arranged on the active area AA and the second diffusion area 156 and the first diffusion area 154 are connected and shared by plural NSET drivers 142. A global metal line 152 arranged in M1 is connected to a contact point 146 of the first diffusion area 154 by a connection 168. Thus, the number of the contact points of the sense amplifier bank can be reduced.

公开(公告)号：JPH11162195A

公开(公告)日：1999-06-18

申请号：JP27007898

申请日：1998-09-24

Applicant: SIEMENS AG ,  IBM

Inventor： KIRIHATA TOSHIAKI ,  WONG HING ,  KRSNIK BOZIDAR

IPC: G01R31/28 ,  G11C11/401 ,  G11C29/04 ,  G11C29/50 ,  G11C29/56 ,  G11C29/00

Abstract: PROBLEM TO BE SOLVED: To realize flexible supervision of a floating condition of a bit line to surely and easily detect a defective bit line, thereby increasing a yield of a module and improving reliability, by utilizing a dummy cycle capable of being controlled in a digital manner. SOLUTION: When a test mode detects cycles of a WriteCAS, a BeforeRAS, and a WCBR to become enable, a pulse signal TEST is periodically reduced to disable an equalizer EQ in a sub-array. When a RAS becomes enable, a readout operation starts. An EQ signal remains in an L condition, and a word line WL and a sense amplifier SA are activated. Accordingly, a bit line BL/BL with leakage is determined. At this time, a cycle timing is determined by a dummy cycle capable of being controlled in a digital manner. When the dummy cycle is terminated and the RAS is disabled, the WL is reset and the SA is disabled, so that the equalizer is reset.

公开(公告)号：JPH11126477A

公开(公告)日：1999-05-11

申请号：JP23189198

申请日：1998-08-18

Applicant: IBM

Inventor： KIRIHATA TOSHIAKI

IPC: G11C11/401 ,  G11C7/10 ,  G11C7/18 ,  G11C11/408 ,  G11C11/409 ,  G11C11/4091 ,  G11C11/4096

Abstract: PROBLEM TO BE SOLVED: To provide a multi-bank DRAM having hierarchical column selection line architecture. SOLUTION: Plural memory cells, which are formed into at least two banks A, B, are provided in a DRAM. Each of banks comprises a memory cell arranged in row and column. The memory cell stores data given by at least one bit line 503 and at least one data line 505. The DRAM is connected to a first switch 507 selecting one bank out of two banks, comprises a second switch 508 selecting one of columns, the first and the second switches 507, 508 couple one of bit lines to one of data lines, and writing data or reading data for a common memory cell for a bank selecting data and a selected column can be performed.

公开(公告)号：JPH10162599A

公开(公告)日：1998-06-19

申请号：JP32111397

申请日：1997-11-21

Applicant: IBM

Inventor： DEBROSSE JOHN ,  KIRIHATA TOSHIAKI ,  WONG HING

IPC: G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a redundancy block architecture configuration using a column redundancy control circuit for reducing a design space effectively. SOLUTION: A column redundancy control circuit RRDN for reducing a design space effectively is constituted in parallel in a word direction and is constituted at the bottom of a redundancy block. The architecture change lays out the redundancy control block effectively by introducing split global buses 41 and 42 that are commonly used with a local column redundancy wire, a half-length one-way column redundancy word line enable signal RWLE for reducing space, and a dispersion word line enable decoder 32 that is designed to utilize the reduced space.

公开(公告)号：JPH07297706A

公开(公告)日：1995-11-10

申请号：JP7024095

申请日：1995-03-28

Applicant: IBM

Inventor： SAN EICHI DON ,  KIRIHATA TOSHIAKI ,  MASHIYUU ROBAATO WAADOMAN

IPC: H03K17/687 ,  G05F3/24 ,  H03K19/0175

Abstract: PURPOSE: To limit a voltage difference between a source node and a gate node to a desired level by providing source and gate nodes to apply voltages and a control means for regulating the voltages to be applied to these nodes. CONSTITUTION: Another element consisting of the voltage driver of a pull-up NMOS transistor(Tr) QN1 is provided with an inverter INV1, PMOSTrs QP2, QP3 and QP4 and NMOSTrs QN5 and QN6. A node 24 is electrically connected with the input of an inverter INV3. The PMOSTrs QP2 and QP3 mutually operate and functionally form a diode 35. Then, this diode maintains the minimum voltage of a node 32 equal to a power supply voltage VDD, when the Tr QP2 is turned on. Further, the Tr QP3 is turned off because of the configuration of this diode 35, and the node 32 reaches a voltage higher than the voltage VDD because of the operation of a voltage-boosting part 23. As a result, the voltage difference between the gate and source of Tr QN1 is limited, and the service life of an off-chip driver 20 is prolonged.

公开(公告)号：JP2004274046A

公开(公告)日：2004-09-30

申请号：JP2004050304

申请日：2004-02-25

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： KIRIHATA TOSHIAKI ,  GOLZ JOHN W

IPC: H01L27/108 ,  G11C11/24 ,  G11C11/401 ,  G11C11/404 ,  H01L21/8242

CPC classification number: G11C11/404 ,  H01L27/108 ,  H01L27/10829

Abstract: PROBLEM TO BE SOLVED: To provide a 2-port DRAM cell consisting of a 2T and 2C (2-transistor and 2-trench-capacitor) DRAM cell formed by combining two 1T (1-transistor and 1-capacitor) DRAM cells.
SOLUTION: The mask data and the cross-sections of the 2T and 2C DRAM cell and those of the 1T DRAM cells are mutually fully compatible except for a diffused connection section where the two memory nodes of the two 1T DRAM cells are connected. Therefore, a true system-on-chip architecture can be formed by completely integrating 1-port memory cells having 1T and 1C DRAM cells with a 2-port memory cell having a 2T and 2C DRAM cell. Alternatively, if the capacitor is reduced to half, random access write cycle time can be further shortened, keeping data maintain time at the same level. If the depth of a trench is reduced to half, a process time in a deep trench can be also shortened.
COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：JP2003242775A

公开(公告)日：2003-08-29

申请号：JP2003056757

申请日：2003-03-04

Applicant: IBM

Inventor： JI BRIAN ,  KIRIHATA TOSHIAKI ,  DIMITRI NETIS

IPC: G11C11/407 ,  G11C7/00 ,  G11C11/401 ,  G11C11/408 ,  G11C11/4097

Abstract: PROBLEM TO BE SOLVED: To provide a method for activating hierarchically word lines. SOLUTION: A memory structure comprises a plurality of banks (each bank comprises a plurality of blocks), a plurality of timing critical address lines (the number of critical address lines is equal to the number of banks) connected to all of the blocks in respective ones of the blocks, and a plurality of dedicated address lines connected to respective ones of the blocks. COPYRIGHT: (C)2003,JPO

公开(公告)号：JP2001068555A

公开(公告)日：2001-03-16

申请号：JP2000210177

申请日：2000-07-11

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： NARAYAN CHANDRASEKHAR ,  ARNDT KENNETH ,  LACHTRUPP DAVID ,  BRINTZINGER AXEL ,  GABRIEL DANIEL ,  KIRIHATA TOSHIAKI

IPC: H01L21/82 ,  H01H85/00 ,  H01H85/02 ,  H01H85/044 ,  H01H85/046 ,  H01L21/66 ,  H01L23/525 ,  H01L27/02

Abstract: PROBLEM TO BE SOLVED: To combine a laser actuation fuse with an electric starting fuse in order to increase total yield of product. SOLUTION: A plurality of different types of fuses 510, each serving a specified purpose, are arranged on a semiconductor integrated circuit wafer, such that a type of fuse can be actuated without missing the function of different types of fuses. A first type of fuse, e.g. a laser actuation fuse, is principally used for repairing a wafer level defect and a second type of fuse, e.g. an electric starting fuse, is used for repairing a defect found after an IC chip is mounted on a module and a stress is applied to the module during burn-in test. The module level defect is an unit cell trouble corrected normally by an electrically programmed fuse, in order to actuate a module level redundancy arrangement.

公开(公告)号：JP2001057085A

公开(公告)日：2001-02-27

申请号：JP2000210249

申请日：2000-07-11

Applicant: IBM

Inventor： KIRIHATA TOSHIAKI ,  DANIEL SUTORASUKA ,  NARAYAN CHANDRASEKHAR ,  WILLIAM TONTEI ,  CLAUDE BARTIN ,  NICK BANHIIRU

IPC: G11C14/00 ,  G11C11/00 ,  G11C16/02 ,  G11C16/04 ,  G11C29/04 ,  H01L21/8246 ,  H01L27/112 ,  G11C29/00

Abstract: PROBLEM TO BE SOLVED: To obtain a partially non-volatile dynamic random access memory(PNDRAM). SOLUTION: A partially non-volatile dynamic random access memory PNDRAM uses a DRAM array formed by plural single transistors 1T cells or two transistors 2T cells. The cell is electrically programmable as a non- volatile memory. Therefore, single chip design characteristic of both of a dynamic random access memory DRAM and an electrically programmable read only memory EPROM can be obtained. A DRAM and an EPROM integrated into a PNDRAM can be always and easily reconstituted during manufacturing or in a market. The PNDRAM has plural applications as a single chip such as a main memory related to ID, BIOS, or operating system information and the like.