公开(公告)号：DE10242877A1

公开(公告)日：2004-03-25

申请号：DE10242877

申请日：2002-09-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ROESNER WOLFGANG ,  RISCH LOTHAR ,  HOFMANN FRANZ ,  SPECHT MICHAEL ,  LEHMANN VOLKER

IPC: H01L21/02 ,  H01L21/334 ,  H01L21/8242 ,  H01L21/84 ,  H01L27/108 ,  H01L27/12 ,  H01L29/94

Abstract: Semiconductor substrate comprises a carrier substrate (1), a semiconductor component layer (3), an insulating layer (2) arranged between the carrier substrate and the semiconductor component layer, recesses (P) formed in a surface facing the insulating layer in the carrier substrate, a dielectric layer (D) formed on the surface of the recesses and carrier substrate, and an electrically conducting layer (E2) formed in the recesses to produce capacitor electrodes. A further electrically conducting layer is formed in the carrier substrate to form capacitor counter electrodes in the region of the recesses. An Independent claim is also included for a process for the production of a semiconductor substrate.

公开(公告)号：DE10241170A1

公开(公告)日：2004-03-18

申请号：DE10241170

申请日：2002-09-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ROESNER WOLFGANG ,  HOFMANN FRANZ ,  SPECHT MICHAEL ,  LANDSGRAF ERHARD ,  LYKEN R JOHANNES

IPC: G11C16/04 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8246 ,  H01L21/8247 ,  H01L21/84 ,  H01L27/115 ,  H01L27/12 ,  H01L29/786 ,  H01L29/788 ,  H01L29/792 ,  H01R11/22 ,  H01R13/62

Abstract: Semiconductor memory having memory cells, each including first and second conductively-doped contact regions and a channel region arranged between the latter, formed in a web-like rib made of semiconductor material and arranged one behind the other in this sequence in the longitudinal direction of the rib. The rib has an essentially rectangular shape with an upper side of the rib and rib side faces lying opposite. A memory layer is configured for programming the memory cell, arranged on the upper side of the rib spaced apart by a first insulator layer, and projects in the normal direction of the one rib side face over one of the rib side faces so that the one rib side face and the upper side of the rib form an edge for injecting charge carriers from the channel region into the memory layer. A gate electrode is spaced apart from the one rib side face by a second insulator layer and from the memory layer by a third insulator layer, electrically insulated from the channel region, and configured to control its electrical conductivity.

公开(公告)号：DE10223709A1

公开(公告)日：2003-12-18

申请号：DE10223709

申请日：2002-05-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LUYKEN JOHANNES R ,  HOFMANN FRANZ ,  ROESNER WOLFGANG

IPC: H01L21/336 ,  H01L29/786

公开(公告)号：DE10121494A1

公开(公告)日：2002-11-14

申请号：DE10121494

申请日：2001-05-03

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HOFMANN FRANZ ,  ROESNER WOLFGANG

IPC: H01L21/8242 ,  H01L29/06 ,  H01L29/78 ,  H01L27/092

Abstract: The invention relates to a MOS transistor in which the source capacity and drain capacity are reduced relatively to the substrate, owing to the fact that an isolating element made of a material with a low dielectric constant is placed under the source and drain supply. The invention also relates to an integrated circuit in which the bitline supply line capacity is reduced relatively to the substrate, owing to the fact that an isolating element made of a material with a low dielectric constant is placed under the bitline supply line.

公开(公告)号：DE10111454A1

公开(公告)日：2002-09-26

申请号：DE10111454

申请日：2001-03-09

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ROESNER WOLFGANG ,  LUYKEN R JOHANNES ,  HOFMANN FRANZ ,  KRETZ JOHANNES

IPC: G11C8/10 ,  G11C13/02 ,  H01L27/108 ,  G11C7/00

Abstract: The memory arrangement has a memory cell field (2) and a decoder circuit for reading from the memory cells (3) with a word line decoder (8), a bit line decoder (11) and a read output (14) for reading out the contents of each individual cell by selecting the word and bit lines corresponding to individual cells. Independent claims are also included for the following: a method of reading from a memory arrangement and a computer arrangement with a processor and memory arrangement.

公开(公告)号：DE10012112C2

公开(公告)日：2002-01-10

申请号：DE10012112

申请日：2000-03-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HOFMANN FRANZ ,  ROESNER WOLFGANG ,  LUYKEN HANNES

IPC: H01L21/336 ,  H01L29/423 ,  H01L29/786 ,  H01L29/78

Abstract: The bar-type field effect transistor consists of a substrate, a bar placed above a substrate and a gate and spacer placed above part of the bar.

公开(公告)号：DE19933565C2

公开(公告)日：2001-11-22

申请号：DE19933565

申请日：1999-07-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHULZ THOMAS ,  ROESNER WOLFGANG

IPC: H01L27/088 ,  H01L27/148 ,  H01L29/423 ,  H01L29/768

公开(公告)号：DE19933565A1

公开(公告)日：2001-02-15

申请号：DE19933565

申请日：1999-07-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHULZ THOMAS ,  ROESNER WOLFGANG

IPC: H01L27/088 ,  H01L27/148 ,  H01L29/423 ,  H01L29/768

Abstract: The semiconductor device includes a first source/drain region, a second source/drain region, and an intermediate channel region, forming a structure made of semiconductor material. The structure comprises a first surface and an opposing second surface. A first gate electrode is arranged on the first surface. A second gate electrode which is driven independently of the first gate electrode is arranged on the second surface. At least part of the channel region is arranged between the first and second gate electrodes. A method of manufacture is also claimed.

公开(公告)号：DE19933564C1

公开(公告)日：2001-01-25

申请号：DE19933564

申请日：1999-07-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHULZ THOMAS ,  ROESNER WOLFGANG ,  FRANOSCH MARTIN ,  SCHAEFER HERBERT ,  RISCH LOTHAR ,  AEUGLE THOMAS

IPC: H01L21/335 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/76 ,  H01L51/00 ,  H01L51/05 ,  H01L51/30 ,  H01L29/78

Abstract: According to the invention, a double gate MOSFET semiconductor layer structure is formed on a substrate (1). This structure is comprised of a first and of a second gate electrode (10A, 10B) between which a semiconductor channel layer zone (4A) is embedded, and of a source region (2A) and a drain region (2B) which are arranged on opposite faces of the semiconductor channel layer zone (4A). At least one additional semiconductor channel layer zone (6A) is provided on one of the gate electrodes (10B). The faces of the at least one additional semiconductor channel layer zone are also contacted by the source region (2A) and drain region (2B).

公开(公告)号：DE102005042317B3

公开(公告)日：2007-04-12

申请号：DE102005042317

申请日：2005-09-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ILICALI GUERKAN ,  ROESNER WOLFGANG

IPC: H01L21/58 ,  B81C3/00 ,  C23C16/40

Abstract: In the production of a layer arrangement (500) by: (a) forming an oxide layer (303) on a first partial layer arrangement (PLA) (300) using non-densified tetraethyl orthosilicate material; (b) forming an additional layer (358) on a second PLA; (c) contacting the PLA's, with the oxide layer and the additional layer having a common interface; and (d) thermally treating, the additional layer formed in step (b) is a nitride layer. Production of a layer arrangement (500) involves: (a) forming an oxide layer (303) on a first partial layer arrangement (PLA) (300) (with at least one layer) using non-densified tetraethyl orthosilicate (TEOS) material; (b) forming an additional layer (358) on a second PLA (with at least one layer); (c) mechanically contacting the first and second PLA's, with the oxide layer on the first PLA and the additional layer on the second PLA having a common interface; and (d) thermally treating the assembly. The additional layer formed in step (b) is a nitride layer. An independent claim is included for the LA formed by the process.