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    Use of context identifiers in cache memory
    45.
    发明专利
    Use of context identifiers in cache memory 未知

    公开(公告)号：AU2003214148A8

    公开(公告)日：2003-10-13

    申请号：AU2003214148

    申请日：2003-03-13

    Applicant: INTEL CORP

    Inventor： HAMMARLUND PER ,  BAKTHA ARAVINDH ,  UPTON MICHAEL ,  VENKATRAMAN K S

    IPC: G06F12/00 ,  G06F12/08 ,  G06F12/10

    Abstract: A context identifier is used in a cache memory apparatus. The context identifier may be written into the tag of a cache line or may be written as an addition to the tag of a cache line, during cache write operation. During a cache read operation, the context identifier of as issued instruction may be compared with the context identifier in the cache line's tag. The cache line's data block may be transferred if the context identifiers and the tags match.

    Rescheduling multiple micro-operations in a processor using replay queue
    46.
    发明专利
    Rescheduling multiple micro-operations in a processor using replay queue 未知

    公开(公告)号：AU3135802A

    公开(公告)日：2002-06-03

    申请号：AU3135802

    申请日：2001-10-18

    Applicant: INTEL CORP

    Inventor： CARMEAN DOUGLAS M ,  BOGGS DARRELL D ,  SAGER DAVID J ,  MCKEEN FRANCIS X ,  HAMMARLUND PER ,  SINGHAL RONAK

    IPC: G06F9/38 ,  G06F9/00

    Abstract: Rescheduling multiple micro-operations in a processor using a replay queue. The processor comprises a replay queue to receive a plurality of instructions and an execution unit to execute the plurality of instructions. A scheduler is coupled between the replay queue and the execution unit. The scheduler speculatively schedules instructions for execution and dispatches each instruction to the execution unit. A checker is coupled to the execution unit to determine whether each instruction has executed successfully. The checker is also coupled to the replay queue to communicate to the replay queue each instruction that has not executed successfully.

    49.
    发明专利
    未知

    公开(公告)号：DE112004001133T5

    公开(公告)日：2006-05-11

    申请号：DE112004001133

    申请日：2004-06-16

    Applicant: INTEL CORP

    Inventor： HAMMARLUND PER ,  CROSSLAND JAMES ,  AGGARWAL ANIL ,  KAUSHIK SHIVNANDAN

    IPC: G06F9/46 ,  G06F9/38 ,  G06F9/50 ,  G06F12/00 ,  G06F12/08 ,  G06F12/14

    Abstract: A method, apparatus, and system are provided for monitoring locks using monitor-memory wait. In one embodiment, a memory to store instructions to perform functions of a monitoring mechanism is provided. The monitoring mechanism having a first logic to cause a processor to exit a sleep state in response to an event, wherein exiting the sleep state comprises resuming control of processing resources that were relinquished by the processor during the sleep state. The monitoring mechanism having a second logic to disable monitoring of a node associated with a contended lock after the processor exits the sleep state.

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