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    一种MEMS薄片及其制造方法
    44.
    发明申请
    一种MEMS薄片及其制造方法 审中-公开

    公开(公告)号：WO2014005496A1

    公开(公告)日：2014-01-09

    申请号：PCT/CN2013/078523

    申请日：2013-06-29

    Applicant: 无锡华润上华半导体有限公司

    Inventor： 代丹 ,  张新伟 ,  周国平 ,  夏长奉

    IPC: B81B7/00 ,  B81C1/00 ,  H01L27/00

    CPC classification number: B81C1/00825 ,  B81B7/0029 ,  B81C1/0038 ,  B81C2201/0167 ,  B81C2201/053

    Abstract: 一种MEMS薄片（100），包括硅衬底层（110）、第一氧化层（120）及第一薄膜层（130）；所述硅衬底层包括用于微机电工艺的正面（112）及与所述正面相对的背面（114），所述正面及所述背面均为抛光面；所述第一氧化层主要成分为二氧化硅，形成于所述硅衬底层的背面；所述第一薄膜层主要成分为氮化硅，形成于所述第一氧化层表面。上述微机电系统薄片中，通过在硅衬底层的背面依次层叠第一氧化层及第一薄膜层，有效保护了背面，防止其在进行微机电工艺过程中划伤，同时还提供了一种MEMS薄片的制造方法。

    PROCESS FOR MINIMIZING CHIPPING WHEN SEPARATING MEMS DIES ON A WAFER
    45.
    发明申请
    PROCESS FOR MINIMIZING CHIPPING WHEN SEPARATING MEMS DIES ON A WAFER 审中-公开
    在微波炉上分离MEMS表面时最小化流动的方法

    公开(公告)号：WO2011140143A1

    公开(公告)日：2011-11-10

    申请号：PCT/US2011/035065

    申请日：2011-05-03

    Applicant: S3C. INC. ,  HORTON, Roger ,  HUSSAIN, Javed

    Inventor： HORTON, Roger ,  HUSSAIN, Javed

    IPC: H01L23/58

    CPC classification number: B81B7/0058 ,  B81C1/00888 ,  B81C2201/053 ,  G01L9/0055 ,  H01L21/78

    Abstract: A method for separating a plurality of dies on a Micro-Electro-Mechanical System (MEMS) wafer comprising scribing a notch on a first side of the wafer between at least two of the plurality of dies on a first surface and depositing a metal on the first surface of the plurality of dies. The method further comprises scribing a second side of the wafer between at least two of the plurality of dies from a second surface thereof through the notch. The first side and second side are substantially parallel and opposite each other and the first surface and the second surface are substantially parallel and opposite each other. In a process in accordance with the present invention, a method to minimize chipping of the bonding portion of a MEMs device during sawing of the wafer is provided, which minimally affects the process steps associated with separating the die on a wafer.

    Abstract translation: 一种用于在微电子机械系统（MEMS）晶片上分离多个管芯的方法，包括在第一表面上的多个管芯中的至少两个之间划定晶片的第一侧上的凹口，并在其上沉积金属 多个管芯的第一表面。 该方法还包括在多个管芯中的至少两个从其第二表面通过切口划分晶片的第二侧。 第一侧面和第二侧面基本上平行且彼此相对，并且第一表面和第二表面基本上平行且彼此相对。 在根据本发明的方法中，提供了一种在晶片切割期间最小化MEM器件的结合部分的碎裂的方法，其最小程度地影响与在晶片上分离晶片相关的工艺步骤。

    MEMS COMPONENT, METHOD FOR PRODUCING A MEMS COMPONENT, AND METHOD FOR HANDLING A MEMS COMPONENT
    46.
    发明申请
    MEMS COMPONENT, METHOD FOR PRODUCING A MEMS COMPONENT, AND METHOD FOR HANDLING A MEMS COMPONENT 审中-公开
    MEMS组件，用于生产MEMS组件和方法用于处理MEMS组件

    公开(公告)号：WO2009092361A2

    公开(公告)日：2009-07-30

    申请号：PCT/DE2009000073

    申请日：2009-01-21

    Applicant: EPCOS AG ,  PAHL WOLFGANG ,  FEIERTAG GREGOR ,  LEIDL ANTON

    Inventor： PAHL WOLFGANG ,  FEIERTAG GREGOR ,  LEIDL ANTON

    IPC: B81B7/00

    CPC classification number: B81C1/00896 ,  B81B7/0061 ,  B81B2201/0257 ,  B81C2201/053 ,  H04R2201/003

    Abstract: The invention relates to a MEMS component comprising a substrate (1) in which at least one cavity (2) is present. The cavity (2) is closed toward an active side of the substrate (1). An inactive side is disposed opposite the active side of the substrate (1), and the substrate (1) is covered by a covering film (3) on the inactive side. The invention further relates to a method for producing a MEMS component comprising the following steps. In the first step, cavities (2) are produced on a substrate wafer (1), wherein the cavities (2) are closed toward an active side and comprise an opening toward an inactive side. In a second step, a covering film (3) is applied to the inactive side of the substrate wafer (1), wherein the covering film (3) is glued to the substrate wafer (1) at least in the area of the substrate wafer (1) between the cavities (2).

    Abstract translation: 本发明提供一种MEMS器件，包括衬底（1），其中，至少一个空腔（2）的存在。 到衬底（1）朝向所述空腔（2）的有源侧是封闭的。 非活动侧被相对地设置在基板（1）和所述衬底的所述有源侧（1）覆盖在非活动侧与盖（3）。 此外，提供了一种制造MEMS器件，其包括以下步骤的方法。 在第一步骤中空腔的基板晶片（1），其中所述空腔（2）被关闭以有源侧并且具有开口到非活动侧上产生（2）。 在第二个步骤中，覆盖箔（3）在所述衬底晶片（1）的非活动侧被施加，其中，所述覆盖膜（3）至少在腔（2）之间的基底晶片（1）的区域到所述衬底晶片 （1）粘接。

    PROCESS FOR INTEGRATING DIELECTRIC OPTICAL COATINGS INTO MICROELECTROMECHANICAL DEVICES
    49.
    发明申请
    PROCESS FOR INTEGRATING DIELECTRIC OPTICAL COATINGS INTO MICROELECTROMECHANICAL DEVICES 审中-公开
    将介电光学涂层集成到微电子设备中的方法

    公开(公告)号：WO02033458A2

    公开(公告)日：2002-04-25

    申请号：PCT/US2001/032512

    申请日：2001-10-17

    IPC: B81B3/00 ,  G02B26/00 ,  G02B6/00

    CPC classification number: B81B3/0083 ,  B81B2201/042 ,  B81B2201/047 ,  B81C1/0038 ,  B81C2201/0159 ,  B81C2201/053 ,  B81C2201/056 ,  G02B26/001

    Abstract: A process for patterning dielectric layers of the type typically found in optical coatings in the context of MEMS manufacturing is disclosed. A dielectric coating is deposited over a device layer, which has or will be released, and patterned using a mask layer. In one example, the coating is etched using the mask layer as a protection layer. In another example, a lift-off process is shown. The primary advantage of photolithographic patterning of the dielectric layers in optical MEMS devices is that higher levels of consistency can be achieved in fabrication, such as size, location, and residual material stress. Competing techniques such as shadow masking yield lower quality features and are difficult to align. Further, the minimum feature size that can be obtained with shadow masks is limited to SIMILAR 100 mu m, depending on the coating system geometry, and they require hard contact with the surface of the wafer.

    Abstract translation: 公开了一种用于在MEMS制造的上下文中通常在光学涂层中发现的类型的介电层图案的工艺。 电介质涂层沉积在器件层上，器件层已经或将被释放，并使用掩模层进行图案化。 在一个实例中，使用掩模层作为保护层来蚀刻涂层。 在另一示例中，示出了剥离过程。 光学MEMS器件中电介质层的光刻图案的主要优点是可以在诸如尺寸，位置和残余材料应力的制造中实现更高水平的稠度。 诸如阴影掩蔽的竞争技术产生较低的质量特征并且难以对准。 此外，根据涂层系统的几何形状，使用荫罩可获得的最小特征尺寸限制为100微米，并且它们需要与晶片的表面硬接触。

    PROTECTIVE COATING ON TRENCH FEATURES OF A WAFER AND METHOD OF FABRICATION THEREOF
    50.
    发明申请
    PROTECTIVE COATING ON TRENCH FEATURES OF A WAFER AND METHOD OF FABRICATION THEREOF 审中-公开
    晶片的特性保护涂层及其制造方法

    公开(公告)号：WO2018002010A1

    公开(公告)日：2018-01-04

    申请号：PCT/EP2017/065787

    申请日：2017-06-27

    Applicant: ROBERT BOSCH GMBH

    Inventor： SUVANTO, Mikko VA

    IPC: B81C1/00 ,  H01L21/78

    CPC classification number: B81B7/0058 ,  B81B2203/033 ,  B81C1/00404 ,  B81C1/00825 ,  B81C1/00896 ,  B81C2201/053 ,  H01L21/78 ,  H01L23/562

    Abstract: A coating for protecting a wafer from moisture and debris due to dicing, singulating, or handling the wafer is provided. A semiconductor sensor device comprises a wafer having a surface and at least one trench feature and the protective coating covering the trench feature. The trench feature comprises a plurality of walls and the walls are covered with the protective coating, wherein the walls of the trench feature are formed as a portion of the semiconductor sensor device. The semiconductor sensor device further comprises a patterned mask formed on the wafer before the trench feature is formed, wherein the protective coating is formed directly to the trench feature and the patterned mask. The semiconductor sensor device is selected from a group consisting of a MEMS die, a sensor die, a sensor circuit die, a circuit die, a pressure die, an accelerometer, a gyroscope, a microphone, a speaker, a transducer, an optical sensor, a gas sensor, a bolometer, a giant megnetoresistive sensor (GMR), a tunnel magnetoresistive (TMR) sensor, an environmental sensor, and a temperature sensor.

    Abstract translation: 提供了用于保护晶片免受由于切割，分离或处理晶片而引起的水分和碎屑的涂层。 半导体传感器装置包括具有表面和至少一个沟槽部件的晶片，并且覆盖沟槽部件的保护涂层。 沟槽特征包括多个壁，并且壁被覆盖有保护涂层，其中沟槽特征的壁被形成为半导体传感器装置的一部分。 半导体传感器器件还包括在形成沟槽特征之前在晶片上形成的图案化掩模，其中保护涂层直接形成到沟槽特征和图案化掩模。 半导体传感器装置选自由MEMS芯片，传感器芯片，传感器电路芯片，电路芯片，压力芯片，加速度计，陀螺仪，麦克风，扬声器，换能器，光学传感器 ，气体传感器，辐射热测量计，巨型磁阻传感器（GMR），隧道磁阻（TMR）传感器，环境传感器和温度传感器。

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