公开(公告)号：KR20100081477A

公开(公告)日：2010-07-15

申请号：KR20090000733

申请日：2009-01-06

Applicant: HYNIX SEMICONDUCTOR INC ,  IUCF HYU

Inventor： GOU JA SEUNG ,  KWON OH KYONG ,  SHIN MIN SEOK ,  KIM MIN KYU

IPC: H03M1/12 ,  H03M1/66

CPC classification number: H03M1/1205 ,  H03F3/45 ,  H03M1/002 ,  H03M1/14 ,  H03M1/66 ,  H03M2201/62

Abstract: PURPOSE: A pipeline ADC is provided to reduce a chip area and power consumption by implementing a sample and hold block and a multiplying DAC into a single circuit in the input end of a pipeline ADC. CONSTITUTION: A calculation amplifier(350) interlinks a positive input end to the ground. A first channel(360) is formed between the output end of the calculation amplifier and a sub input end. A second channel(370) is formed between the output terminal of a calculation amplifier and the sub input end. A control signal supplying part(380) determines the connection form between an analog signal input end, a reference voltage input end, and the calculation amplifier.

Abstract translation: 目的：提供流水线ADC，通过将采样和保持模块和乘法DAC组合到流水线ADC输入端的单个电路来减少芯片面积和功耗。 构成：计算放大器（350）将正输入端与地相互连接。 第一通道（360）形成在计算放大器的输出端和副输入端之间。 在计算放大器的输出端子和副输入端之间形成第二通道（370）。 控制信号提供部分（380）确定模拟信号输入端，参考电压输入端和计算放大器之间的连接形式。

公开(公告)号：KR20100081476A

公开(公告)日：2010-07-15

申请号：KR20090000732

申请日：2009-01-06

Applicant: HYNIX SEMICONDUCTOR INC ,  IUCF HYU

Inventor： GOU JA SEUNG ,  KWON OH KYONG ,  SHIN MIN SEOK ,  KIM MIN KYU

IPC: H03M1/12 ,  H03M1/66

CPC classification number: H03M1/14 ,  H03M1/122 ,  H03M1/361 ,  H03M1/662 ,  H03M2201/2216 ,  H03M2201/62

Abstract: PURPOSE: A pipeline ADC is provided to reduce power consumption by reducing the number of a MDAC(Multiplying Digital to Analog Converter). CONSTITUTION: A calculation amplifier(350) interlinks a positive input end to the ground. A first channel(360) is formed between the output end of a calculation amplifier and a negative input end. A second channel(370) is formed between the output end and a sub input end. An input selection part(380) determines a first channel, a second channel, a connection state between an analog signal input end and a reference voltage input end. A control signal supplying part(390) controls a first channel, a second channel, the connected state of the input selection part.

Abstract translation: 目的：提供流水线ADC，通过减少MDAC（乘数数模转换器）的数量来降低功耗。 构成：计算放大器（350）将正输入端与地相互连接。 第一通道（360）形成在计算放大器的输出端和负输入端之间。 在输出端和子输入端之间形成第二通道（370）。 输入选择部分（380）确定第一通道，第二通道，模拟信号输入端和参考电压输入端之间的连接状态。 控制信号提供部分（390）控制第一通道，第二通道，输入选择部件的连接状态。

公开(公告)号：KR1020090071705A

公开(公告)日：2009-07-02

申请号：KR1020070139576

申请日：2007-12-28

Applicant: 인하대학교 산학협력단

Inventor： 윤광섭 ,  손영준

IPC: H03M1/12

CPC classification number: H03M1/121 ,  H03M1/002 ,  H03M1/361 ,  H03M2201/2216 ,  H03M2201/62

Abstract: An analog to digital converter is provided to reduce power consumption and a chip size by reducing a configuration device using the reference voltage selecting circuit. A voltage divider(100) divides the reference voltage by using a resistor. A reference voltage selecting switch(200) is connected to the output terminal of the voltage divider and varies the output voltage by selecting the reference voltage generated from the voltage divider. A sample-hold switch unit(300) receives an analog input signal and outputs the sampling signal and the hold signal of the analog input signal. A comparator receives the output signal of the sample-hold switch unit and the output voltage of the reference voltage selecting switch unit and compares the output voltage and the output signal. A preamplifier(500) amplifies the output signal according to the comparison result of the comparator and compensates for the error due to the amplification. A switch controller controls the reference voltage selecting switch unit by generating the reference voltage control signal.

Abstract translation: 提供了一种模数转换器，通过减少使用参考电压选择电路的配置装置来降低功耗和芯片尺寸。 分压器（100）通过使用电阻器对参考电压进行分压。 参考电压选择开关（200）连接到分压器的输出端，并通过选择从分压器产生的参考电压来改变输出电压。 采样保持开关单元（300）接收模拟输入信号并输出​​模拟输入信号的采样信号和保持信号。 比较器接收采样保持开关单元的输出信号和参考电压选择开关单元的输出电压，并比较输出电压和输出信号。 前置放大器（500）根据比较器的比较结果放大输出信号，并补偿由于放大引起的误差。 开关控制器通过产生参考电压控制信号来控制参考电压选择开关单元。

公开(公告)号：KR1020070095675A

公开(公告)日：2007-10-01

申请号：KR1020060026172

申请日：2006-03-22

Applicant: 엘지전자 주식회사

Inventor： 정소영

IPC: H03M3/02

CPC classification number: H03M3/32 ,  H03M3/322 ,  H03M2201/62 ,  H03M2201/932

Abstract: A delta sigma modulator is provided to reduce size and current consumption while maintaining resolution by reducing the size of an integration capacitor. A delta sigma modulator includes an amplifying unit, and unit integrators. The amplifying unit adjusts amplification degree according to the ratio of sampling capacitors and integration capacitors. The unit integrators have switches which constitute the paths of the capacitors and the amplifying unit. The size of the sampling capacitor which constitutes the unit integrator of the last end, is smaller than the sampling capacitor of the adjacent unit integrator.

Abstract translation: 提供Δ-Σ调制器以通过减小积分电容器的尺寸来减小尺寸和电流消耗，同时保持分辨率。 ΔΣ调制器包括放大单元和单元积分器。 放大单元根据采样电容器和积分电容器的比例来调节放大率。 单元积分器具有构成电容器和放大单元的路径的开关。 构成最后一端的单位积分器的采样电容器的尺寸小于相邻单元积分器的采样电容器。

公开(公告)号：KR200415365Y1

公开(公告)日：2006-05-02

申请号：KR2020060004924

申请日：2006-02-22

Applicant: 주식회사 다넷시스

Inventor： 권성원

IPC: H03M1/66 ,  H04B7/24

CPC classification number: H03M1/66 ,  H03M2201/196 ,  H03M2201/61 ,  H03M2201/62 ,  H03M2201/932

Abstract: 디지털-아날로그 변환기가 개시된다. 다수의 디지털 제어신호들에 응답하여 아날로그 전압들을 발생시키기 위한 디지털-아날로그 변환기는 아날로그 전압들을 출력하기 위한 제1단자, 및 제2단자 사이에 직렬로 접속된 다수의 제1저항들, 각각이 상기 직렬로 접속된 다수의 제1저항들 중에서 대응되는 두 개의 저항들 사이에 형성된 다수의 노드들, 및 다수의 제2저항들을 구비하며, 상기 다수의 제2저항들 각각의 제1단은 상기 제1단자, 상기 다수의 노드들 중에서 대응되는 노드, 및 상기 제2단자에 접속되고, 상기 다수의 제2저항들 각각의 제2단은 대응되는 디지털 제어신호를 수신한다. 본 고안에 따른 디지털-아날로그 변환기는 다수의 저항들로만 구성되므로, 다수의 반도체 소자들을 구비하는 종래의 디지털-아날로그 변환기에 비해 통신회선의 주파수 특성 변화에 신속하게 반응하고, 저전력 소모 및 통신장치의 소형화가 가능하며, 불량률도 낮다.
DAC, 디지털-아날로그 변환기, 모뎀, 통신장치

公开(公告)号：KR1020050017914A

公开(公告)日：2005-02-23

申请号：KR1020030055460

申请日：2003-08-11

Applicant: 학교법인 포항공과대학교

Inventor： 장영찬 ,  박상훈 ,  박홍준

IPC: H03M1/00

CPC classification number: H03M1/1215 ,  H03M1/002 ,  H03M2201/62

Abstract: PURPOSE: A CMOS time interleaved flash analog/digital converter apparatus of a single input buffer is provided to reduce power consumption and offset of an input buffer. CONSTITUTION: According to the CMOS time interleaved flash analog/digital converter apparatus, an input buffer(10) shares an input buffer receiving an analog signal as one input buffer. The first 1-GS/s 4-bit flash analog/digital converters(ADC)(20-1 to 20-8) converts the analog signal provided from the input buffer into a digital signal. A multiple phase clock generator(30) provides a phase clock to the first 1-GS/s 4-bit flash ADC using a phase locked loop(PLL).

Abstract translation: 目的：提供单个输入缓冲器的CMOS时间交错闪存模拟/数字转换器装置，以减少输入缓冲器的功耗和偏移。 构成：根据CMOS时间交错闪存模拟/数字转换装置，输入缓冲器（10）将接收模拟信号的输入缓冲器共享为一个输入缓冲器。 第一个1-GS / s 4位闪存模拟/数字转换器（ADC）（20-1至20-8）将从输入缓冲器提供的模拟信号转换为数字信号。 多相时钟发生器（30）使用锁相环（PLL）向第一个1-GS / s 4位闪存ADC提供相位时钟。

公开(公告)号：KR1020000014801A

公开(公告)日：2000-03-15

申请号：KR1019980034385

申请日：1998-08-25

Applicant: 현대반도체 주식회사

Inventor： 이용섭

IPC: H03M1/16

CPC classification number: H03M1/48 ,  H03M1/007 ,  H03M2201/62 ,  H03M2201/93

Abstract: PURPOSE: An analog-digital convertor is provided to reduce a layout area by using basically embedded program memory and general purpose register. CONSTITUTION: A central processing unit(202) has a program memory(204) storing an analog-digital converting program and a general purpose register(206) storing a digital signal generated at an execution process of the analog-digital converting program. A digital-analog convertor(208) converts a digital signal outputted from the general purpose register into an analog signal. A comparator(210) receives a sampled analog input signal as a comparison signal and an output signal from the digital-analog signal as a reference signal, and outputs a comparison result of the comparison signal and the reference signal to the program memory.

Abstract translation: 目的：提供模拟数字转换器，通过使用基本嵌入式程序存储器和通用寄存器来减少布局面积。 构成：中央处理单元（202）具有存储模拟数字转换程序和存储在模拟数字转换程序的执行过程中生成的数字信号的通用寄存器（206）的程序存储器（204）。 数字模拟转换器（208）将从通用寄存器输出的数字信号转换为模拟信号。 比较器（210）将作为比较信号的采样模拟输入信号和来自数字 - 模拟信号的输出信号作为参考信号接收，并将比较信号和参考信号的比较结果输出到程序存储器。

公开(公告)号：KR1020150052686A

公开(公告)日：2015-05-14

申请号：KR1020130134406

申请日：2013-11-06

Applicant: 한국과학기술원

Inventor： 류승탁 ,  김종인 ,  민기정

IPC: H03M1/12

CPC classification number: H03M1/122 ,  H03M1/002 ,  H03M1/203 ,  H03M2201/62 ,  H03M2201/6309 ,  H03M2201/718

Abstract: 복수개의제 1 래치를구비하고, 각제 1 래치는상기아날로그신호에대응되는아날로그입력전압및 각기준전압을입력받고제 1 클록에따라두 전압차이를증폭하여제 1 차동 (+)출력과제 1 차동 (-)출력을출력하는제 1 래치단; 복수개의제 2 래치를구비하고, 하나의제 1 래치의차동출력을각각 (+),(-)입력단으로입력받는제 2 래치및 어느하나의제 1 래치의제 1 차동 (-)출력과상기제 1 래치의기준전압과인접한낮은기준전압을수신하는인접제 1 래치의제 1 차동 (+)출력을각각 (+),(-)단자로입력받는제 2 래치를포함하는제 2 래치단; 및복수개의 SR래치를구비하고, 어느하나의제 2 래치의 (-)출력값과상기어느하나의제 2 래치의인접한하위제 2 래치의 (+)출력값을수신하여인터폴레이션출력을생성하는제 3 SR 래치단을포함하는아날로그디지털변환기를제공한다.

Abstract translation: 提供了一种模拟数字转换器。 模拟数字转换器包括：第一锁存器，其包括第一锁存器，并且每个第一锁存器接收对应于模拟信号和每个参考电压的模拟输入电压，根据第一时钟放大两个电压之间的差，并输出 第一差分（+）输出和第一差分（ - ）输出; 第二锁存器，其具有从（+）和（ - ）输入端接收第一锁存器的差分输出的第二锁存器和接收第一锁存器的第一差分（ - ）输出和第一差分（+ ）输出接收低参考电压的相邻第一锁存器和第一锁存器的参考电压; 以及第三SR锁存器，其包括SR锁存器，并通过接收第二锁存器的（ - ）输出值和与第二锁存器相邻的下部第二锁存器的（+）输出值产生插值输出。

公开(公告)号：KR1020140085883A

公开(公告)日：2014-07-08

申请号：KR1020120155695

申请日：2012-12-28

Applicant: 주식회사 레이믹스

Inventor： 정성재 ,  이정은 ,  이주호 ,  김진화

IPC: H03M1/12 ,  H03M3/02

CPC classification number: H03M3/478 ,  H03M1/18 ,  H03M2201/6107 ,  H03M2201/62

Abstract: According to a time continuous sigma-delta analog-to-digital converter capable of controlling an operable input signal magnitude range, and a control method therefor in accordance to a preferred embodiment of the present invention, the input signal magnitude range can be adjusted by varying an input resistance value when a magnitude of an input signal changes. According to a preferred embodiment of the present invention, the time continuous sigma-delta analog-to-digital converter capable of controlling an operable input signal magnitude range comprises: a loop filter including at least one amplifier; a quantizing unit for quantizing a signal outputted from the loop filter into N bits; a signal detecting unit to detect an output of the quantizing unit; and a control unit to control a magnitude range of an operable input signal of the converter using the signal detected on the signal detecting unit.

Abstract translation: 根据能够控制可操作输入信号幅度范围的时间连续Σ-Δ模数转换器及其根据本发明的优选实施例的控制方法，可以通过改变输入信号幅度范围来调节输入信号幅度范围 当输入信号的幅度变化时的输入电阻值。 根据本发明的优选实施例，能够控制可操作输入信号幅度范围的时间连续Σ-Δ模数转换器包括：包括至少一个放大器的环路滤波器; 用于将从环路滤波器输出的信号量化为N位的量化单元; 信号检测单元，用于检测量化单元的输出; 以及控制单元，其使用在所述信号检测单元上检测到的信号来控制所述转换器的可操作输入信号的幅度范围。

公开(公告)号：KR101286226B1

公开(公告)日：2013-07-15

申请号：KR1020120019876

申请日：2012-02-27

Applicant: 한국과학기술원

Inventor： 이상국 ,  조홍수 ,  장영신 ,  한석균

IPC: H03M1/66 ,  G09G3/36

CPC classification number: H03M1/66 ,  G09G3/36 ,  G09G5/006 ,  H03M2201/62 ,  H03M2201/932

Abstract: PURPOSE: A digital analog converter, a driving apparatus including the same, and a display apparatus are provided to remove the loading effect without any additional current. CONSTITUTION: A digital analog converter (1500) comprises an R- DAC (Digital to Analog Converter) (1510, 1520, 1530) connected with a cascade and a buffer (1540). The R- DAC (1510) comprises multiple resistance strings (R1) and a decoder (1512). The R-DAC (1520) comprises multiple resistance strings (R2) which connected to the R-DAC (1510) and a decoder (1522). The R-DAC (1530) comprises multiple resistance strings (R3) which connected to the R-DAC (1520) and a decoder (1532). The buffer is connected to the output terminal of the R-DAC (1530). [Reference numerals] (1512,1532) Four bits decoder; (1522) Two bits decoder

Abstract translation: 目的：提供数字模拟转换器，包括该数字模拟转换器的驱动装置和显示装置，以便在没有任何附加电流的情况下去除负载效应。 构成：数字模拟转换器（1500）包括与级联连接的R-DAC（数模转换器）（1510,1520,1530）和缓冲器（1540）。 R-DAC（1510）包括多个电阻串（R1）和解码器（1512）。 R-DAC（1520）包括连接到R-DAC（1510）的多个电阻串（R2）和解码器（1522）。 R-DAC（1530）包括连接到R-DAC（1520）的多个电阻串（R3）和解码器（1532）。 缓冲器连接到R-DAC（1530）的输出端。 （附图标记）（1512,1532）四位解码器; （1522）两位解码器