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    METHOD OF MANUFACTURING A CHIP SUPPORT BOARD STRUCTURE
    51.
    发明申请
    METHOD OF MANUFACTURING A CHIP SUPPORT BOARD STRUCTURE 有权
    制造支持板结构的方法

    公开(公告)号：US20140115888A1

    公开(公告)日：2014-05-01

    申请号：US13663333

    申请日：2012-10-29

    Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

    Inventor： Ting-Hao Lin ,  Yu-Te Lu ,  De-Hao Lu

    IPC: H05K3/06

    CPC classification number: H05K1/056 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/13 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49894 ,  H01L2924/0002 ,  H05K1/0204 ,  H05K2201/029 ,  H05K2201/0323 ,  H05K2201/09054 ,  H05K2203/0323 ,  H05K2203/0384 ,  H05K2203/063 ,  Y10T29/49117 ,  Y10T29/49121 ,  Y10T29/49124 ,  Y10T29/49155 ,  Y10T29/49156 ,  H01L2924/00

    Abstract: A method of manufacturing a chip support board structure which includes the steps of forming a metal substrate structure, forming a photo resist pattern, etching the metal substrate structure to form a paddle, removing the photo resist pattern, pressing an insulation layer against the paddle, polishing the insulation layer, forming a circuit layer and forming a solder resist is disclosed. The metal substrate structure is formed by sandwiching a block layer with two metal substrate layers, multilayer. The metal substrate structure is etched under control to an effective depth such that each paddle thus formed has the same shape and depth. Therefore, the method of the present invention can be widely applied to the general mass production processes to effectively solve the problems in the prior arts due to depth differences, such offset, position mismatch and peeling off in the chip support board.

    Abstract translation: 一种制造芯片支撑板结构的方法，其包括以下步骤：形成金属基板结构，形成光致抗蚀剂图案，蚀刻金属基板结构以形成桨，去除光致抗蚀剂图案，将绝缘层压靠在桨上， 公开了抛光绝缘层，形成电路层和形成阻焊剂。 金属基板结构是通过将具有两个金属基底层的多层的阻挡层夹在中间而形成的。 在控制下将金属基底结构蚀刻到有效深度，使得如此形成的每个桨具有相同的形状和深度。 因此，本发明的方法可以广泛地应用于通常的批量生产过程，以有效地解决由于芯片支撑板中的深度差异，偏移，位置失配和剥离等现有技术的问题。

    METHOD OF THIN PRINTED CIRCUIT BOARD WET PROCESS CONSISTENCY ON THE SAME CARRIER
    52.
    发明申请
    METHOD OF THIN PRINTED CIRCUIT BOARD WET PROCESS CONSISTENCY ON THE SAME CARRIER 有权
    薄印刷电路板湿法方法在相同载体上的一致性

    公开(公告)号：US20130270216A1

    公开(公告)日：2013-10-17

    申请号：US13448478

    申请日：2012-04-17

    Applicant: CHENG-HSIUNG YANG

    Inventor： CHENG-HSIUNG YANG

    IPC: H05K3/00 ,  B32B38/10 ,  B05D5/12

    CPC classification number: H05K3/0085 ,  H05K1/0393 ,  H05K3/0008 ,  H05K2201/10424 ,  H05K2203/167

    Abstract: A method of thin printed circuit board wet process consistency on the same carrier, and more particularly to a printed circuit board in the developing, copper plating, stripping, etching and other wet processes uses the same frame as a carrier from the beginning to the end of the wet process, such that the thin printed circuit board is conducted a continuous and automatic wet process to avoid disassembly, storage and transportation between each process. Moreover, when using the flame, the thin printed circuit board is smooth and flattening in the wet process for avoiding “water effect,” the effective area is not exposed to any mechanical members for preventing scratches, and there are point contacts between the thin printed circuit board and the frame for preventing chemical residue. Accordingly, the present invention can not only enhance the yield of the thin printed circuit board but also shorten the production time.

    Abstract translation: 一种薄印刷电路板在相同载体上湿法稠度的方法，更具体地说涉及在显影，镀铜，剥离，蚀刻和其它湿法工艺中的印刷电路板，从开始到结束使用与载体相同的框架 使得薄的印刷电路板进行连续和自动的湿法，以避免在每个工艺之间的拆卸，储存和运输。 此外，当使用火焰时，薄的印刷电路板在湿法中平滑且扁平化以避免“水分效应”，有效区域不暴露于任何机械构件以防止划伤，并且薄印刷 电路板和防止化学残留物的框架。 因此，本发明不仅可以提高薄印刷电路板的产量，而且缩短生产时间。

    METHOD OF MANUFACTURING A LAMINATE CIRCUIT BOARD WITH A MULTILAYER CIRCUIT STRUCTURE
    53.
    发明申请
    METHOD OF MANUFACTURING A LAMINATE CIRCUIT BOARD WITH A MULTILAYER CIRCUIT STRUCTURE 审中-公开
    制造具有多层电路结构的层压板电路板的方法

    公开(公告)号：US20130219713A1

    公开(公告)日：2013-08-29

    申请号：US13663663

    申请日：2012-10-30

    Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

    Inventor： Jun-Chung Hsu ,  Chi-Ming Lin ,  Tso-Hung Yeh ,  Ya-Hsiang Chen

    IPC: H05K3/46

    CPC classification number: H05K3/4644 ,  H05K3/24 ,  H05K3/4682 ,  H05K2201/0317 ,  H05K2201/0347 ,  H05K2203/072 ,  Y10T29/49155

    Abstract: A method of manufacturing a laminate circuit board with a multilayer circuit structure which includes the steps of forming a metal layer on a substrate, patterning the metal layer to form a circuit metal layer, forming a nanometer plating layer on the circuit metal layer, forming a cover layer to cover the substrate and the nanometer plating layer, forming through holes in the cover layer to generate openings exposing part of the nanometer plating layer, and finally forming a second metal layer on the cover layer to fill up the openings is disclosed. The nanometer plating layer is used to obtain same effect of previously roughening by chemical bonding, such that no circuit width is reserved for compensation, and the density of the circuit increases such that much more dense circuit can be implemented.

    Abstract translation: 一种制造具有多层电路结构的叠层电路板的方法，包括以下步骤：在基板上形成金属层，图案化金属层以形成电路金属层，在电路金属层上形成纳米电镀层，形成 盖层覆盖基板和纳米镀层，在盖层中形成孔，以产生露出纳米镀层的一部分的开口，最后在覆盖层上形成第二金属层以填充开口。 纳米电镀层用于通过化学键合获得与之前的粗糙化相同的效果，使得没有电路宽度被保留用于补偿，并且电路的密度增加，使得可以实现更加密集的电路。

    Double layer circuit board
    57.
    发明授权
    Double layer circuit board 有权

    公开(公告)号：US10440836B2

    公开(公告)日：2019-10-08

    申请号：US15138261

    申请日：2016-04-26

    Applicant: Kinsus Interconnect Technology Corp.

    Inventor： Ting-Hao Lin ,  Chiao-Cheng Chang ,  Yi-Nong Lin

    IPC: H05K1/02 ,  H05K1/11 ,  H05K3/42 ,  H05K3/00 ,  H05K3/46

    Abstract: Provided is a double layer circuit board and a manufacturing method thereof. The double layer circuit board comprises a substrate, a first circuit layer formed on a first surface of the substrate, a second circuit layer formed on a second surface of the substrate, and at least one connecting pillar formed in and covered by the substrate. Each one of the at least one connecting pillar includes a first end connected to the first circuit layer and a second end connected to the second circuit layer. A terminal area of the second end is greater than a terminal area of the first end. Therefore, the second circuit layer is firmly connected to the first circuit layer through the at least one connecting pillar. A yield rate of the double layer circuit board may be increased.

    Multi-layer circuit board capable of being applied with electrical testing and method for manufacturing the same
    58.
    发明授权
    Multi-layer circuit board capable of being applied with electrical testing and method for manufacturing the same 有权

    公开(公告)号：US10334719B2

    公开(公告)日：2019-06-25

    申请号：US15826692

    申请日：2017-11-30

    Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

    Inventor： Chin-Kuan Liu ,  Chao-Lung Wang ,  Shuo-Hsun Chang ,  Yu-Te Lu ,  Chin-Hsi Chang

    IPC: H05K1/02 ,  H05K1/09 ,  H05K3/46 ,  H05K3/06

    Abstract: A multi-layer circuit board capable of being applied with electrical testing includes a patterned metal-interface layer, a metallic delivery loading plate, an electrical connection layer, a conductive corrosion-barrier layer, a bottom dielectric layer, and a multi-layer circuit structure. The multi-layer circuit structure is disposed on the delivery loading plate through the bottom dielectric layer. The top-layer circuit of the multi-layer circuit structure is electrically connected to the conductive corrosion-barrier layer through the bottom-layer circuit and the electrical connection layer. The delivery loading plate and the patterned metal-interface layer expose the conductive corrosion-barrier layer. Therefore, before the multi-layer circuit board is packaged, an electrical testing can be applied to the multi-layer circuit board to check if it can be operated normally. Hence, costs for figuring out reasons of the unqualified electronic component can be reduced, and responsibilities for the unqualified electrical testing result of the electronic component can be clarified.

    Buildup board structure
    59.
    发明授权
    Buildup board structure 有权

    公开(公告)号：US10256028B2

    公开(公告)日：2019-04-09

    申请号：US15086333

    申请日：2016-03-31

    Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

    Inventor： Ting-Hao Lin ,  Chiao-Cheng Chang ,  Yi-Nong Lin

    IPC: H01F27/28 ,  H05K1/03 ,  H05K1/11 ,  H05K1/16 ,  H05K3/46

    Abstract: A buildup board structure incorporating magnetic induction coils and flexible boards is disclosed. The buildup board structure includes at least one first, second and third buildup bodies modular and stackable. Any two adjacent buildup bodies are separated by a covering layer provided with a central hole for electrical insulation. All central holes are aligned. Each buildup body includes a plurality of flexible boards, and each flexible board is embedded with a plurality of magnetic induction coils surrounding the corresponding central hole and connected through connection pads. The first, second and third buildup bodies are easily laminated in any order by any number as desired such that the effect of magnetic induction provided by the magnetic induction coils embedded in the buildup board structure are addable to greatly enhance the overall effect of magnetic induction.

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