Abstract:
A method of manufacturing a chip support board structure which includes the steps of forming a metal substrate structure, forming a photo resist pattern, etching the metal substrate structure to form a paddle, removing the photo resist pattern, pressing an insulation layer against the paddle, polishing the insulation layer, forming a circuit layer and forming a solder resist is disclosed. The metal substrate structure is formed by sandwiching a block layer with two metal substrate layers, multilayer. The metal substrate structure is etched under control to an effective depth such that each paddle thus formed has the same shape and depth. Therefore, the method of the present invention can be widely applied to the general mass production processes to effectively solve the problems in the prior arts due to depth differences, such offset, position mismatch and peeling off in the chip support board.
Abstract:
A method of thin printed circuit board wet process consistency on the same carrier, and more particularly to a printed circuit board in the developing, copper plating, stripping, etching and other wet processes uses the same frame as a carrier from the beginning to the end of the wet process, such that the thin printed circuit board is conducted a continuous and automatic wet process to avoid disassembly, storage and transportation between each process. Moreover, when using the flame, the thin printed circuit board is smooth and flattening in the wet process for avoiding “water effect,” the effective area is not exposed to any mechanical members for preventing scratches, and there are point contacts between the thin printed circuit board and the frame for preventing chemical residue. Accordingly, the present invention can not only enhance the yield of the thin printed circuit board but also shorten the production time.
Abstract:
A method of manufacturing a laminate circuit board with a multilayer circuit structure which includes the steps of forming a metal layer on a substrate, patterning the metal layer to form a circuit metal layer, forming a nanometer plating layer on the circuit metal layer, forming a cover layer to cover the substrate and the nanometer plating layer, forming through holes in the cover layer to generate openings exposing part of the nanometer plating layer, and finally forming a second metal layer on the cover layer to fill up the openings is disclosed. The nanometer plating layer is used to obtain same effect of previously roughening by chemical bonding, such that no circuit width is reserved for compensation, and the density of the circuit increases such that much more dense circuit can be implemented.
Abstract:
A method for selectively processing a surface tension of a solder mask layer in a circuit board is provided. The method conducts surface tension processing to the flip-chip area and the non-flip-chip area of the solder mask layer in the circuit board. Therefore, the underfill used in packaging configures relative contact angles at the flip-chip area and the non-flip-chip area of the solder mask layer, respectively. In such a way, the present invention is adapted to solve the difficulties of the underfill void bulb and the overflowing contamination at the same time.
Abstract:
A package structure preventing solder overflow on substrate solder pads includes a plurality of die pins, a plurality of solders and a plurality of substrate solder pads. The die pins are located under a die. The substrate solder pads are formed on an upper surface of a substrate by copper plating or etching. Each of the substrate solder pads has at least one solder pad connection point. The solders connect the die pins with the corresponding solder pad connection points, respectively. Each of the solder pad connection points has a pair of solder pad ridges or a pair of solder pad grooves. The solder pad ridges and the solder pad grooves filled with the solder or a resin can prevent the solder overflow problem.
Abstract:
A multi-layer circuit structure is disposed on the delivery loading plate through the bottom-layer circuit structure, the delivery loading plate exposes the conductive corrosion-barrier layer, and the top-layer circuit of the multi-layer circuit structure is electrically connected to the conductive corrosion-barrier layer through the bottom-layer circuit and the electrical connection layer. Therefore, before the multi-layer circuit board is delivered to the assembly company or before the multi-layer circuit board is packaged with chips, an electrical testing can be applied to the multi-layer circuit board.
Abstract:
Provided is a double layer circuit board and a manufacturing method thereof. The double layer circuit board comprises a substrate, a first circuit layer formed on a first surface of the substrate, a second circuit layer formed on a second surface of the substrate, and at least one connecting pillar formed in and covered by the substrate. Each one of the at least one connecting pillar includes a first end connected to the first circuit layer and a second end connected to the second circuit layer. A terminal area of the second end is greater than a terminal area of the first end. Therefore, the second circuit layer is firmly connected to the first circuit layer through the at least one connecting pillar. A yield rate of the double layer circuit board may be increased.
Abstract:
A multi-layer circuit board capable of being applied with electrical testing includes a patterned metal-interface layer, a metallic delivery loading plate, an electrical connection layer, a conductive corrosion-barrier layer, a bottom dielectric layer, and a multi-layer circuit structure. The multi-layer circuit structure is disposed on the delivery loading plate through the bottom dielectric layer. The top-layer circuit of the multi-layer circuit structure is electrically connected to the conductive corrosion-barrier layer through the bottom-layer circuit and the electrical connection layer. The delivery loading plate and the patterned metal-interface layer expose the conductive corrosion-barrier layer. Therefore, before the multi-layer circuit board is packaged, an electrical testing can be applied to the multi-layer circuit board to check if it can be operated normally. Hence, costs for figuring out reasons of the unqualified electronic component can be reduced, and responsibilities for the unqualified electrical testing result of the electronic component can be clarified.
Abstract:
A buildup board structure incorporating magnetic induction coils and flexible boards is disclosed. The buildup board structure includes at least one first, second and third buildup bodies modular and stackable. Any two adjacent buildup bodies are separated by a covering layer provided with a central hole for electrical insulation. All central holes are aligned. Each buildup body includes a plurality of flexible boards, and each flexible board is embedded with a plurality of magnetic induction coils surrounding the corresponding central hole and connected through connection pads. The first, second and third buildup bodies are easily laminated in any order by any number as desired such that the effect of magnetic induction provided by the magnetic induction coils embedded in the buildup board structure are addable to greatly enhance the overall effect of magnetic induction.
Abstract:
Provided is a landless multilayer circuit board and a manufacturing method thereof. The manufacturing method includes steps of forming a first circuit on a first substrate, patterning a photoresist layer to form at least one via between the first circuit and a second circuit, forming at least one connecting pillar in the at least one via, removing the photoresist layer, forming a second substrate to cover the at least one connect pillar, and forming the second circuit on the second substrate. The second circuit is connected to the first circuit through the at least one connecting pillar. When the second circuit is formed, the at least one via does not need to be filled, thereby making the second circuit flat.