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公开(公告)号：KR1019950004853B1
公开(公告)日：1995-05-15
申请号：KR1019910014100
申请日：1991-08-14
Applicant: 삼성전자주식회사
IPC: G11C11/407
CPC classification number: G11C8/12
Abstract: The device has a number of main blocks that are each subdivided into a number of sub-blocks that are separately activated. Block selectors use line and column address signals to identify specific locations. The line address signals are tied to specific inputs of AND gates, such that combinations may be sued to identify specific memory blocks. Once selected, the column address signals may be used to identify locations within the blocks.
Abstract translation: 该设备具有多个主块，每个主块分别被分成多个分别激活的子块。 块选择器使用行和列地址信号来标识特定位置。 线路地址信号被连接到与门的特定输入端，使得组合可以被起诉以识别特定的存储器块。 一旦选择，列地址信号可以用于识别块内的位置。
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公开(公告)号：KR100069650B1
公开(公告)日：1994-01-10
申请号：KR1019910002606
申请日：1991-02-19
Applicant: 삼성전자주식회사
IPC: G11C11/407
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公开(公告)号：KR1019930001739B1
公开(公告)日：1993-03-12
申请号：KR1019890020105
申请日：1989-12-29
Applicant: 삼성전자주식회사
IPC: G11C11/34
Abstract: The twisted word line for preventing the scramble of signal transmission in a memory array comprises a polysilicon layer (GP) connected to the gate of a MOS transistor and arranged parallel with one another, and a low resistance of metal layer (ME) coupled to the polysilicon layer. The memory array includes a number of cells having MOS transistors and capacitors, a number of bit lines and a number of word lines. The metal layer (ME1) of first word line (WL1) is twisted at least one time with the metal layer (ME2) of second word line (WL2) adjacent to the first word line (WL1). The polysilicon lines (GP1-GP4) and metal lines (ME1-ME4) are coupled through contact regions (C1,C2,C3,C4).
Abstract translation: 用于防止存储器阵列中的信号传输扰乱的扭转字线包括连接到MOS晶体管的栅极并彼此平行布置的多晶硅层（GP），并且耦合到所述MOS晶体管的金属层（ME）的低电阻 多晶硅层。 存储器阵列包括具有MOS晶体管和电容器的多个单元，多个位线和多个字线。 第一字线（WL1）的金属层（ME1）与邻近第一字线（WL1）的第二字线（WL2）的金属层（ME2）至少扭曲一次。 多晶硅线（GP1-GP4）和金属线（ME1-ME4）通过接触区（C1，C2，C3，C4）耦合。
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Patent Agency Ranking
公开(公告)号：KR1019930001738B1
公开(公告)日：1993-03-12
申请号：KR1019890020104
申请日：1989-12-29
Applicant: 삼성전자주식회사
IPC: G11C11/34
Abstract: A memory cell array comprises a memory matrix including memory cells, word lines and bit lines, word line drivers and row address decoders. The arranging method comprises partitioning the word line drivers into a number of word line driver groups and staggering the word line driver groups to allow denser packing of the memory cell array since larger chip area is provided for each word line driver. In increasing the pitch of the word line drivers, increased design margins may be allowed in the layout of the memory device.
Abstract translation: 存储单元阵列包括存储单元，字线和位线，字线驱动器和行地址解码器的存储矩阵。 排列方法包括将字线驱动器划分成多个字线驱动器组，并交错字线驱动器组以允许更密集的存储单元阵列的打包，因为为每个字线驱动器提供了更大的芯片面积。 在增加字线驱动器的音调时，可能在存储器件的布局中允许增加的设计余量。
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公开(公告)号：KR1019920010346B1
公开(公告)日：1992-11-27
申请号：KR1019900007388
申请日：1990-05-23
Applicant: 삼성전자주식회사
IPC: G11C11/407
CPC classification number: G11C7/065
Abstract: The sense amplifier driver circuit for reducing the noise and improving the stability uses a switched driver transistor (Q10) connected between an external voltage (Vcc) and an earth (Vss) and an associated bias circuit including a MOSFET (Q11) which forms a current miller circuit with the driver transistor (Q10), to raise the peak current of the sense amplifier driving signal. A constant current source has a MOSFET (Q14) supplied with bias voltage (Vbias) at its gate lying between the externl voltage (Vcc) and the earth voltage (Vss). The bias circuit controls the gate voltage of the driver transistor (Q10) for increasing the peak current of the sense amplifier driving signal.
Abstract translation: 用于降低噪声和提高稳定性的读出放大器驱动器电路使用连接在外部电压（Vcc）和地（Vss）之间的开关驱动晶体管（Q10）和包括形成电流的MOSFET（Q11）的相关偏置电路 铣刀电路与驱动晶体管（Q10），以提高读出放大器驱动信号的峰值电流。 恒流源具有在位于外部电压（Vcc）和接地电压（Vss）之间的栅极处提供偏置电压（Vbias）的MOSFET（Q14）。 偏置电路控制用于增加读出放大器驱动信号的峰值电流的驱动晶体管（Q10）的栅极电压。
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公开(公告)号：KR1019920010344B1
公开(公告)日：1992-11-27
申请号：KR1019890020108
申请日：1989-12-29
Applicant: 삼성전자주식회사
IPC: G11C11/34
CPC classification number: G11C5/063 , G11C8/14 , H01L23/5222 , H01L23/5225 , H01L23/528 , H01L2924/0002 , H01L2924/00
Abstract: The memory array comprises a number of word lines (WL), a number of word line drivers (10) for driving the word lines and a number of row address decoders for driving the word line drivers. Each of the word line drivers is connected to a group of four neighboring word lines of the word lines. The four neighboring word lines of the group are twisted across each other so that each one of the four neighboring word lines is not continually adjacent to its adjacent neighboring word line. The word line drivers are equally spaced and arranged in an alternating pattern on both sides of the memory array. The array minimises the word line coupling noise.
Abstract translation: 存储器阵列包括多个字线（WL），用于驱动字线的多个字线驱动器（10）和用于驱动字线驱动器的多个行地址解码器。 每个字线驱动器连接到字线的四个相邻字线的一组。 组中的四个相邻字线彼此扭曲，使得四个相邻字线中的每一个不是连续地邻近其相邻的相邻字线。 字线驱动器在存储器阵列的两侧上以等间距排列成交替图案。 该阵列使字线耦合噪声最小化。
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