公开(公告)号：KR1020150132661A

公开(公告)日：2015-11-26

申请号：KR1020140058402

申请日：2014-05-15

Applicant: 삼성전자주식회사

Inventor： 유우경 ,  백종민 ,  안상훈 ,  라상호 ,  이내인

IPC: H01L21/31 ,  H01L21/768 ,  H01L21/764

CPC classification number: H01L21/7682 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02208 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/02345 ,  H01L21/02348 ,  H01L21/311 ,  H01L21/31144 ,  H01L21/76834 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

Abstract: 반도체장치및 그제조방법이제공된다. 반도체장치제조방법은기판상에층간절연막을형성하되, 상기층간절연막의상부는상기층간절연막의하부보다높은포어(pore) 밀도를가지며, 상기층간절연막의중간부는상기층간절연막의상부를향할수록점진적으로증가하는상기포어밀도를갖는것; 및상기층간절연막을관통하는도전패턴들을형성하는것을포함할수 있다. 상기도전패턴들사이에는에어갭이제공될수 있다.

Abstract translation: 提供半导体器件及其制造方法。 半导体器件制造方法在衬底上形成层间绝缘膜，其中层间绝缘膜的上部具有比层间绝缘膜的下部更高的孔密度，并且层间绝缘膜的中间部分具有逐渐增加的孔密度 朝向层间绝缘膜的上部。 半导体器件制造方法包括形成穿透层间绝缘膜的导电图案。 可以在导电图案之间设置气隙。

公开(公告)号：KR1020150116517A

公开(公告)日：2015-10-16

申请号：KR1020140041159

申请日：2014-04-07

Applicant: 삼성전자주식회사

Inventor： 안상훈 ,  라상호 ,  백종민 ,  유우경 ,  이내인

IPC: H01L21/768 ,  H01L21/60

CPC classification number: H01L23/53295 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76826 ,  H01L21/76832 ,  H01L21/76835 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: 본발명은반도체장치및 이의제조방법을제공한다. 이반도체장치에서는콘택/비아플러그와접하는하부도전패턴옆에도에어갭 영역이배치된다. 이제조방법에서는도전패턴들사이를채우는희생막을형성하고상부배선공정을진행한후에희생막을선택적으로제거한다.

Abstract translation: 本发明提供一种半导体器件及其制造方法。 气隙区域布置在半导体器件的邻近接触触点和通孔插头的下导电图案的区域中。 制造方法形成牺牲膜，通过该牺牲膜填充导电图案之间的间隙，并且在上部布线处理之后选择性地消除牺牲膜。

公开(公告)号：KR1020150078100A

公开(公告)日：2015-07-08

申请号：KR1020130167196

申请日：2013-12-30

Applicant: 삼성전자주식회사

Inventor： 백종민 ,  라상호 ,  안상훈 ,  유우경 ,  이내인

IPC: H01L21/28

CPC classification number: H01L23/528 ,  H01L21/7682 ,  H01L21/76834 ,  H01L23/5222 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: 본발명은반도체장치및 이의제조방법을제공한다. 이장치에서는다양한간격의배선들사이에에어갭영역이존재하고배선들상에투과막이존재한다.

Abstract translation: 本发明的主题是提供能够提高信号传输速度的半导体器件。 本发明提供半导体器件及其制造方法。 在具有各种间隔的导线之间存在气隙区域，并且在导线上存在透射膜。

公开(公告)号：KR1020130114484A

公开(公告)日：2013-10-18

申请号：KR1020120036902

申请日：2012-04-09

Applicant: 삼성전자주식회사

Inventor： 백종민 ,  박인선 ,  이종명 ,  홍종원 ,  김회승 ,  윤정수

IPC: H01L21/3205 ,  H01L21/28

CPC classification number: H01L21/76802 ,  H01L21/76804 ,  H01L21/76814 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76844 ,  H01L21/76885

Abstract: PURPOSE: A method for manufacturing a semiconductor device is provided to increase an aspect ratio by forming self-aligned top conductive patterns. CONSTITUTION: Switching elements are formed on a substrate. A bottom structure is formed on the substrate. A bottom conductive layer is formed on the bottom structure (S10). Sacrificial mask patterns are formed on the bottom conductive layer (S15). Bottom conductive patterns and top conductive patterns are formed in opening parts (S40). [Reference numerals] (S10) Bottom conductive film is formed; (S15) Sacrificial mask patterns are formed; (S20) Bottom conductive patterns are formed by etching the bottom conductive film; (S25) Inter-layer insulation film is formed between layers; (S30) Sacrificial mask patterns are exposed by flattening the inter-layer insulation film; (S35) Opening parts are formed by removing the exposed sacrificial mask patterns; (S40) Top conductive patterns are formed in the opening parts; (S5) Bottom insulation film is formed on a substrate

Abstract translation: 目的：提供一种用于制造半导体器件的方法，以通过形成自对准的顶部导电图案来增加纵横比。 构成：开关元件形成在基板上。 在基板上形成底部结构。 在底部结构上形成底部导电层（S10）。 牺牲掩模图案形成在底部导电层上（S15）。 底部导电图案和顶部导电图案形成在开口部分中（S40）。 （附图标记）（S10）形成底部导电膜; （S15）形成牺牲掩模图案; （S20）通过蚀刻底部导电膜形成底部导电图案; （S25）层之间形成层间绝缘膜; （S30）通过使层间绝缘膜变平而露出牺牲掩模图案; （S35）通过去除曝光的牺牲掩模图案形成开口部分; （S40）在开口部形成有顶部导电图案， （S5）在基板上形成底部绝缘膜

公开(公告)号：KR1020120030782A

公开(公告)日：2012-03-29

申请号：KR1020100092514

申请日：2010-09-20

Applicant: 삼성전자주식회사

Inventor： 한규희 ,  안상훈 ,  이장희 ,  백종민 ,  김경희 ,  박병률 ,  김병희

IPC: H01L21/768

CPC classification number: H01L23/481 ,  H01L21/76801 ,  H01L21/76825 ,  H01L21/76831 ,  H01L21/76898 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/14181 ,  H01L2224/16146 ,  H01L2924/00014 ,  H01L2224/05552

Abstract: PURPOSE: A method for forming a through silicon via using a low dielectric material is provided to deduce the RC delay of an electric signal by forming an inter-metal dielectric layer and a via insulation film contiguous to a TSV(Through Silicon Via) into a low dielectric insulator layer. CONSTITUTION: A semiconductor substrate is etched and a first via hole is formed(S100). A low dielectric insulator layer filling the first via hole is deposited(S200). A second via hole is formed by etching a part of a low dielectric insulator layer in the first via hole. A via insulation film consisting of the low dielectric insulator layer and an inter metal dielectric are simultaneously formed on an upper part of the semiconductor substrate(S400). A metal layer filling the second via hole is deposited(S600). The metal layer on the upper part of the semiconductor substrate is removed(S700).

Abstract translation: 目的：提供一种通过使用低电介质材料形成穿硅的方法，通过将与TSV（通过硅通孔）相邻的金属间介电层和通孔绝缘膜形成为电导信号的RC延迟，从而推导出电信号的RC延迟 低介电绝缘体层。 构成：蚀刻半导体衬底并形成第一通孔（S100）。 沉积填充第一通孔的低介电绝缘体层（S200）。 通过蚀刻第一通孔中的低介电绝缘体层的一部分来形成第二通孔。 在半导体基板的上部同时形成由低介电绝缘体层和金属间介电体构成的通孔绝缘膜（S400）。 沉积填充第二通孔的金属层（S600）。 去除半导体衬底上部的金属层（S700）。

公开(公告)号：KR1020090111932A

公开(公告)日：2009-10-28

申请号：KR1020080037556

申请日：2008-04-23

Applicant: 삼성전자주식회사

Inventor： 차태호 ,  정성희 ,  최길현 ,  김병희 ,  박희숙 ,  백종민

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L29/42324 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/10873 ,  H01L29/4941 ,  H01L29/517

Abstract: PURPOSE: A gate structures and a method of forming the same are provided to improve the thermal stability and the electrical characteristic by forming an Ohmic layer pattern with a high melting point metal like the titanium. CONSTITUTION: A gate structure comprises a gate insulating layer(110) on a substrate, a poly silicon layer on the gate insulating layer, an Ohmic layer on the poly silicon layer, a diffusion barrier on the Ohmic layer, an amorphous silicon on the diffusion barrier, and a metal layer on the amorphous silicon. The method of manufacturing a gate structure is as follows. The gate insulating layer is formed on the substrate. The poly silicon layer is formed on the gate insulating layer. The Ohmic layer is formed on the poly silicon layer. The diffusion barrier is formed on the Ohmic layer. The amorphous silicon layer is formed on the diffusion barrier. The metal layer is formed on the amorphous silicon layer.

Abstract translation: 目的：提供一种栅极结构及其形成方法，以通过形成具有像钛这样的高熔点金属的欧姆层图案来提高热稳定性和电特性。 构成：栅极结构包括在基板上的栅极绝缘层（110），栅极绝缘层上的多晶硅层，多晶硅层上的欧姆层，欧姆层上的扩散阻挡层，扩散层上的非晶硅 阻挡层和非晶硅上的金属层。 栅极结构的制造方法如下。 栅极绝缘层形成在基板上。 多晶硅层形成在栅极绝缘层上。 欧姆层形成在多晶硅层上。 扩散阻挡层在欧姆层上形成。 在扩散阻挡层上形成非晶硅层。 金属层形成在非晶硅层上。

公开(公告)号：KR1020070109078A

公开(公告)日：2007-11-15

申请号：KR1020060041578

申请日：2006-05-09

Applicant: 삼성전자주식회사

Inventor： 박종희 ,  김기석 ,  백종민 ,  황현철 ,  양성은 ,  진성현

IPC: H01L21/68

CPC classification number: H01L21/68735 ,  H01L21/67201 ,  H01L21/68742 ,  Y10S414/139 ,  Y10S414/141

Abstract: A load lock station for preventing a sliding state of a wafer is provided to prevent a breakdown of the wafer and a generation of particles by loading the wafer on a stable loading position. A load lock station includes a station having a place on which a wafer is loaded, and a wafer guide installed around the station in order to guide a loading position of the wafer and to prevent a sliding state of the wafer. The wafer guide has an inclined inside facing the wafer. The wafer guide is installed at a predetermined distance from an edge end of the wafer loaded on a normal loading position of the station. The station is formed with a first station(110) having two opposite station members facing each other to load left and right edges of a first wafer and a second station(120) for loading a second wafer. The wafer guide is formed with a first wafer guide(112) for guiding a loading operation of the first wafer and preventing a sliding state of the first wafer, and a second wafer guide(122) for guiding a loading operation of the second wafer and preventing a sliding state of the second wafer.

Abstract translation: 提供一种用于防止晶片滑动状态的负载锁定站，以通过将晶片载入稳定的装载位置来防止晶片的破坏和颗粒的产生。 负载锁定站包括具有装载晶片的位置的台站以及安装在工位周围的晶片引导件，以引导晶片的装载位置并防止晶片的滑动状态。 晶片引导件具有面向晶片的倾斜内部。 晶片引导件安装在距加载在工位的正常装载位置的晶片的边缘端预定的距离处。 该站形成有具有彼此面对的两个相对站构件的第一站（110），以加载第一晶片的左边缘和右边缘，以及用于加载第二晶片的第二站（120）。 晶片引导件形成有用于引导第一晶片的加载操作并防止第一晶片的滑动状态的第一晶片引导件（112）和用于引导第二晶片的加载操作的第二晶片引导件（122） 防止第二晶片的滑动状态。

公开(公告)号：KR100764652B1

公开(公告)日：2007-10-08

申请号：KR1020060103830

申请日：2006-10-25

Applicant: 삼성전자주식회사

Inventor： 백종민

IPC: H04B1/40 ,  G06F3/0489

CPC classification number: G06F3/04886

Abstract: An apparatus and a method for inputting keys of a terminal having a touch screen are provided to enhance user convenience by solving a problem that when a key is inputted, the region of an output screen image is reduced. A display unit(222) outputs a background image or a screen image of an executed application, and when a key input event occurs, the display unit(222) outputs a translucent keyboard on the background image or the image of the application in an overlap manner. A touch sensing unit(224) is positioned on the display unit(222) and senses a touch. When the key input event occurs, a controller(200) outputs the keyboard on the screen image outputted from the display unit(222) in the overlap manner and checks whether the touch sensed by the touch sensing unit(224) is for key input. If the touch is for a key input, the controller(200) controls so as to receive a key of the position corresponding to the touch and output the same to the display unit(222).

Abstract translation: 提供一种用于输入具有触摸屏的终端的键的装置和方法，以通过解决当输入键时减少输出屏幕图像的区域的问题来提高用户便利性。 显示单元（222）输出执行的应用的背景图像或屏幕图像，并且当键输入事件发生时，显示单元（222）以重叠的方式在背景图像或应用的图像上输出半透明键盘 方式。 触摸感测单元（224）位于显示单元（222）上并感测触摸。 当键输入事件发生时，控制器（200）以重叠的方式从显示单元（222）输出的屏幕图像上输出键盘，并检查由触摸感测单元（224）感测的触摸是否用于键输入。 如果触摸用于键输入，则控制器（200）控制以接收与触摸相对应的位置的键，并将其输出到显示单元（222）。

公开(公告)号：KR1020060128081A

公开(公告)日：2006-12-14

申请号：KR1020050048947

申请日：2005-06-08

Applicant: 삼성전자주식회사

Inventor： 백종민 ,  김기석 ,  박종희 ,  황현철

IPC: H01L21/205

CPC classification number: C23C16/45563 ,  C23C16/4401 ,  H01L21/67017

Abstract: A pipe system and a semiconductor manufacturing apparatus are provided to prevent adhesion of a solid by-product. A pipe system includes a process chamber(110). A trap(130) removes a solid by-product included in exhaust gas from the process chamber. A first pipe(170a) connects a process chamber to the trap. A first heater encloses the first pipe. A second pipe connects a pump to the trap. At least one nozzle supplies gas in the first pipe through the first heater and the first pipe. At least one nozzle has a portion protruding into the interior of the pipe and is deflected toward the forward direction of the flow of the fluid in the interior of the first pipe, and the end of the nozzle and the deflected portion are located in the interior of the first pipe.

Abstract translation: 提供管道系统和半导体制造装置以防止固体副产物的粘附。 管道系统包括处理室（110）。 捕集器（130）除去来自处理室的废气中包含的固体副产物。 第一管（170a）将处理室连接到捕集器。 第一个加热器包围第一个管道。 第二根管将泵连接到陷阱。 至少一个喷嘴通过第一加热器和第一管道在第一管道中提供气体。 至少一个喷嘴具有突出到管内部的部分并且朝向第一管内部的流体流的向前方向偏转，并且喷嘴的端部和偏转部分位于内部 的第一根管子。

公开(公告)号：KR1020060124441A

公开(公告)日：2006-12-05

申请号：KR1020050046369

申请日：2005-05-31

Applicant: 삼성전자주식회사

Inventor： 황현철 ,  이승배 ,  백종민

IPC: H01L21/304

CPC classification number: H01L21/67028 ,  H01L21/67103

Abstract: A semiconductor fabricating apparatus with a module heater is provided to prevent particles from being generated by remaining impurities in the center of a shower head by including a heater module in which a heater block capable of transferring heat to the center of the shower head is installed in a head part. A head part is installed in the upper part of a reaction chamber. A shower head introduces reaction gas or cleaning gas into the reaction chamber, installed in the head part. A module heater is installed in the head part, composed of first, second and third heater blocks(52a,52b,52c). The first heater block is formed on the center of the shower head. The second heater block surrounds the outer circumference of the first heater block. The third heater block surrounds the outer circumference of the second heater block. The first, the second and the third heater block are ring types.

Abstract translation: 提供具有模块加热器的半导体制造装置，通过包括加热器模块来防止在淋浴喷头的中心残留杂质而产生颗粒，在该加热器模块中，能够将热量传递到淋浴头的中心的加热器组件 一个头部。 头部安装在反应室的上部。 淋浴头将反应气体或清洁气体引入反应室，安装在头部。 模块加热器安装在由第一，第二和第三加热器块（52a，52b，52c）组成的头部中。 第一加热器块形成在淋浴头的中心。 第二加热器块围绕第一加热器块的外圆周。 第三加热器块围绕第二加热器块的外圆周。 第一，第二和第三加热器块是环型。