公开(公告)号：WO2005017964A2

公开(公告)日：2005-02-24

申请号：PCT/US2004025152

申请日：2004-08-04

Applicant: IBM ,  CHEN HUAJIE ,  CHIDAMBARRAO DURESETI ,  GLUSCHENKOV OLEG G ,  STEEGEN AN L ,  YANG HAINING S

Inventor： CHEN HUAJIE ,  CHIDAMBARRAO DURESETI ,  GLUSCHENKOV OLEG G ,  STEEGEN AN L ,  YANG HAINING S

IPC: H01L21/20 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L

CPC classification number: H01L21/84 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: A p-type field effect transistor (PFET) and an n-type field effect transistor (NFET) of an integrated circuit are provided. A first strain is applied to the channel region of the PFET but not the NFET via a lattice-mismatched semiconductor layer such as silicon germanium disposed in source and drain regions of only the PFET and not of the NFET. A process of making the PFET and NFET is provided. Trenches are etched in the areas to become the source and drain regions of the PFET and a lattice-mismatched silicon germanium layer is grown epitaxially therein to apply a strain to the channel region of the PFET adjacent thereto. A layer of silicon can be grown over the silicon germanium layer and a salicide formed from the layer of silicon to provide low-resistance source and drain regions.

Abstract translation: 提供集成电路的p型场效应晶体管（PFET）和n型场效应晶体管（NFET）。 第一应变施加到PFET的沟道区，而不是NFET通过位于仅仅PFET而不是NFET的源极和漏极区域中的晶格不匹配的半导体层，例如硅锗。 提供制造PFET和NFET的工艺。 在区域中蚀刻沟槽以成为PFET的源极和漏极区域，并且将晶格失配的硅锗层外延生长以向与其相邻的PFET的沟道区域施加应变。 可以在硅锗层上生长一层硅层，并从硅层形成硅化物以提供低电阻源极和漏极区域。

公开(公告)号：WO2012118568A3

公开(公告)日：2012-11-08

申请号：PCT/US2012020728

申请日：2012-01-10

Applicant: IBM ,  TEKLEAB DANIEL G ,  HUNG TRAN H ,  SLEIGHT JEFFREY W ,  CHIDAMBARRAO DURESETI

Inventor： TEKLEAB DANIEL G ,  HUNG TRAN H ,  SLEIGHT JEFFREY W ,  CHIDAMBARRAO DURESETI

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/78 ,  B82Y10/00 ,  H01L29/0676 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/775 ,  H01L29/7827

Abstract: A nanotubular MOSFET device and a method of fabricating the same are used to extend device scaling roadmap while maintaining good short channel effects and providing competitive drive current. The nanotubular MOSFET device includes a concentric tubular inner (61) and outer gate (50) separated from each other by a tubular shaped epitaxially grown silicon layer, and a source (35) and drain (31) respectively separated by spacers (51, 41) surrounding the tubular inner and outer gates. The method of forming the nanotubular MOSFET device includes: forming on a substrate a cylindrical shaped Si layer (30); forming an outer gate surrounding the cylindrical Si layer (30) and positioned between a bottom spacer (41) and a top spacer (51); growing a silicon epitaxial layer on the top spacer adjacent to a portion of the cylindrical shaped Si layer; etching an inner portion of the cylindrical shaped Si forming a hollow cylinder; forming an inner spacer at the bottom of the inner cylinder; forming an inner gate by filling a portion of the hollow cylinder; forming a sidewall spacer adjacent to the inner gate; and etching a deep trench for accessing and contacting the outer gate and drain.

Abstract translation: 纳米管MOSFET器件及其制造方法用于扩展器件缩放路线图，同时保持良好的短沟道效应并提供有竞争力的驱动电流。 纳米管MOSFET器件包括通过管状外延生长硅层彼此分离的同心管状内部（61）和外部栅极（50），以及分别由间隔物（51,41）分隔的源极（35）和漏极（31） ）围绕管状内门和外门。 形成纳米管MOSFET器件的方法包括：在衬底上形成圆柱形的Si层（30）; 形成围绕所述圆柱形Si层（30）并定位在底部间隔物（41）和顶部间隔物（51）之间的外部门; 在与圆柱形Si层的一部分相邻的顶部间隔上生长硅外延层; 蚀刻形成中空圆筒的圆柱形Si的内部; 在内筒的底部形成内隔板; 通过填充中空圆筒的一部分形成内门; 形成邻近所述内门的侧壁间隔物; 并蚀刻用于访问和接触外部栅极和漏极的深沟槽。

公开(公告)号：WO2007016183A3

公开(公告)日：2008-12-18

申请号：PCT/US2006029069

申请日：2006-07-26

Applicant: IBM ,  CHIDAMBARRAO DURESETI ,  JORDAN DONALD L ,  MCCULLEN JUDITH H ,  ONSONGO DAVID M ,  WAGNER TINA ,  WILLIAMS RICHARD Q

Inventor： CHIDAMBARRAO DURESETI ,  JORDAN DONALD L ,  MCCULLEN JUDITH H ,  ONSONGO DAVID M ,  WAGNER TINA ,  WILLIAMS RICHARD Q

IPC: G06F7/48

CPC classification number: G06F17/5068 ,  G06F17/5036 ,  H01L29/7843

Abstract: System and method for compact model algorithms (310-350) to accurately account for effects of layout-induced changes in nitride liner (260) stress in semiconductor devices (200). The layout- sensitive compact model algorithms (310-350) account for the impact of large layout variation on circuits by implementing algorithms for obtaining the correct stress response approximations and layout extraction algorithms for obtaining the correct geometric parameters that drive the stress response. In particular, these algorithms include specific information from search "buckets" that are directionally-oriented and include directionally-specific distance measurements for analyzing in detail the specific shape neighborhood of the semiconductor device. The algorithms are additionally adapted to enable the modeling and stress impact determination of a device having single stress liner film and dual-stress liners (260) (two different liner films that abut at an interface).

Abstract translation: 用于紧凑模型算法（310-350）的系统和方法来准确地说明半导体器件（200）中氮化物衬垫（260）应力的布局引起的变化的影响。 布局敏感的紧凑模型算法（310-350）通过实现用于获得正确的应力响应近似和布局提取算法的算法来解决大布局变化对电路的影响，以获得驱动应力响应的正确几何参数。 特别地，这些算法包括来自定向定向的搜索“桶”的特定信息，并且包括用于详细分析半导体器件的特定形状邻域的定向特定的距离测量。 这些算法还适用于能够确定具有单个应力衬垫膜和双应力衬垫（260）（在界面处邻接的两个不同衬垫膜）的器件的建模和应力冲击测定。

公开(公告)号：WO2005057612A3

公开(公告)日：2008-01-03

申请号：PCT/US2004020904

申请日：2004-06-30

Applicant: IBM ,  CHIDAMBARRAO DURESETI ,  DOKUMACI OMER H ,  GLUSCHENKOV OLEG G

Inventor： CHIDAMBARRAO DURESETI ,  DOKUMACI OMER H ,  GLUSCHENKOV OLEG G

IPC: H01L21/8238 ,  H01L21/311 ,  H01L21/76 ,  H01L21/82 ,  H01L21/84 ,  H01L27/12 ,  H01L29/24 ,  H01L29/808

CPC classification number: H01L29/1608 ,  H01L21/8213 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/1095 ,  H01L29/66651 ,  H01L29/7378 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/7849 ,  H01L29/8086

Abstract: A semiconductor structure and method of manufacturing is provided. The method of manufacturing includes forming shallow trench isolation (STI) (25) in a substrate and providing a first material (30) and a second material (40) on the substrate. The first material (30) and the second material (40) are mixed into the substrate by a thermal anneal process to form a first island (50) and second island (55) at an nFET region and a pFET region, respectively. A layer of different material is formed on the first island (50) and the second island (55). The STI relaxes and facilitates the relaxation of the first island (50) and the second island (55). The first material (30) may be deposited or grown Ge material and the second material (40) may deposited or grown Si:C or C. A strained Si layer is formed on at least one of the first island (50) and the second island (55).

Abstract translation: 提供半导体结构和制造方法。 制造方法包括在衬底中形成浅沟槽隔离（STI）（25），并在衬底上提供第一材料（30）和第二材料（40）。 通过热退火工艺将第一材料（30）和第二材料（40）混合到衬底中，以在nFET区域和pFET区域分别形成第一岛（50）和第二岛（55）。 在第一岛（50）和第二岛（55）上形成不同材料层。 STI放松并促进第一个岛屿（50）和第二个岛屿（55）的放松。 可以将第一材料（30）沉积或生长Ge材料，并且第二材料（40）可以沉积或生长Si：C或C.在第一岛（50）和第二岛（50）中的至少一个上形成应变Si层 岛（55）。

公开(公告)号：WO2007038237A3

公开(公告)日：2007-07-26

申请号：PCT/US2006036916

申请日：2006-09-22

Applicant: IBM ,  CHIDAMBARRAO DURESETI ,  DOKUMACI OMER ,  GLUSCHENKOV OLEG ,  BELYANSKY MICHAEL

Inventor： CHIDAMBARRAO DURESETI ,  DOKUMACI OMER ,  GLUSCHENKOV OLEG ,  BELYANSKY MICHAEL

IPC: H01L21/28 ,  H01L29/40

CPC classification number: H01L29/512 ,  H01L21/26586 ,  H01L21/31155 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66583

Abstract: The present invention provides a semiconductor structure having at least one CMOS device in which the Miller capacitances, i-e., overlap capacitances, are reduced and the drive current is improved. The inventive structure includes a semiconductor substrate having at least one overlaying gate conductor, each of the at least one overlaying gate conductors has vertical edges; a first gate oxide located beneath the at least one overlaying gate conductor, the first gate oxide not extending beyond the vertical edges of the at least overlaying gate conductor; and a second gate oxide located beneath at least a portion of the at one overlaying gate conductor. In accordance with the present invention, the first gate oxide and the second gate oxide are selected from high k oxide-containing materials and low k oxide-containing materials, and the first gate oxide is higher k than the second gate oxide or vice-versa.

Abstract translation: 本发明提供一种半导体结构，其具有至少一个CMOS器件，其中米勒电容，即重叠电容，并且驱动电流得到改善。 本发明的结构包括具有至少一个覆盖栅极导体的半导体衬底，所述至少一个覆盖栅极导体中的每一个具有垂直边缘; 位于所述至少一个覆盖栅极导体下方的第一栅极氧化物，所述第一栅极氧化物不延伸超过所述至少覆盖栅极导体的垂直边缘; 以及位于一个重叠栅极导体的至少一部分下方的第二栅极氧化物。 根据本发明，第一栅极氧化物和第二栅极氧化物选自含高K氧化物的材料和低K氧化物的材料，并且第一栅极氧化物比第二栅极氧化物高k，反之亦然 。

公开(公告)号：WO2005079182A3

公开(公告)日：2006-04-06

申请号：PCT/US2004001721

申请日：2004-01-22

Applicant: IBM ,  BEINTNER JOCHEN ,  CHIDAMBARRAO DURESETI ,  DIVKARUNI RAMACHANDRA

Inventor： BEINTNER JOCHEN ,  CHIDAMBARRAO DURESETI ,  DIVKARUNI RAMACHANDRA

IPC: H01L29/786 ,  H01L21/336 ,  H01L21/8238

CPC classification number: H01L29/78642 ,  H01L21/2257 ,  H01L29/66787

Abstract: A new class of high-density, vertical Fin-FET devices that exhibit low contact resistance is described. These vertical Fin-FET devices have vertical silicon "fins" (12A) that act as the transistor body. Doped source and drain regions (26A, 28A) are formed at the bottoms and tops, respectively, of the fins (12A). Gates (24A, 24B) are formed along sidewalls of the fins. Current flows vertically through the fins (12A) between the source and drain regions (26A, 28A) when an appropriate bias is applied to the gates (24A, 24B). An integrated process for forming pFET, nFET, multi-fin, single-fin, multi-gate and double-gate vertical Fin-FETs simultaneously is described.

Abstract translation: 描述了一种新型的具有低接触电阻的高密度垂直Fin-FET器件。 这些垂直Fin-FET器件具有用作晶体管体的垂直硅“鳍”（12A）。 掺杂的源极和漏极区域（26A，28A）分别形成在鳍片（12A）的底部和顶部。 盖板（24A，24B）沿翅片的侧壁形成。 当适当的偏压被施加到栅极（24A，24B）时，电流垂直地流过源极和漏极区域（26A，28A）之间的鳍片（12A）。 描述了同时形成pFET，nFET，多鳍，单鳍，多栅极和双栅极垂直鳍FET的集成工艺。

公开(公告)号：WO2005050701A8

公开(公告)日：2005-11-03

申请号：PCT/US2004037434

申请日：2004-11-09

Applicant: IBM ,  DORIS BRUCE B ,  BELYANSKY MICHAEL P ,  BOYD DIANE C ,  CHIDAMBARRAO DURESETI ,  GLUSCHENKOV OLEG

Inventor： DORIS BRUCE B ,  BELYANSKY MICHAEL P ,  BOYD DIANE C ,  CHIDAMBARRAO DURESETI ,  GLUSCHENKOV OLEG

IPC: H01L21/8238 ,  H01L31/119 ,  H01L21/302 ,  H01L21/336 ,  H01L21/461 ,  H01L31/113

CPC classification number: H01L29/7845 ,  H01L21/26513 ,  H01L21/28035 ,  H01L21/28167 ,  H01L21/28247 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823842 ,  H01L29/1083 ,  H01L29/4925 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659

Abstract: A method of fabricating a semiconductor device structure, includes: providing a substrate (1), providing an electrode (6) on the substrate (1), forming a recess (12) in the electrode (6), the recess having an opening, disposing a small grain semiconductor material (17) within the recess, covering the opening to contain the small grain semiconductor material, within the recess, and then annealing the resultant structure.

Abstract translation: 一种制造半导体器件结构的方法，包括：提供衬底（1），在所述衬底（1）上提供电极（6），在所述电极（6）中形成凹部（12），所述凹部具有开口， 在凹部内设置小晶粒半导体材料（17），在凹部内覆盖开口以容纳小晶粒半导体材料，然后对所得结构进行退火。

公开(公告)号：WO2005043591A8

公开(公告)日：2005-11-03

申请号：PCT/US2004034562

申请日：2004-10-19

Applicant: IBM ,  CHIDAMBARRAO DURESETI ,  DOKUMACI OMER ,  CHEN HUAJIE

Inventor： CHIDAMBARRAO DURESETI ,  DOKUMACI OMER ,  CHEN HUAJIE

IPC: H01L20060101 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/01 ,  H01L27/12 ,  H01L29/10 ,  H01L

CPC classification number: H01L29/7848 ,  H01L21/3081 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/1054 ,  H01L29/66628 ,  H01L29/66636 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device and method of manufacturing a semiconductor device. The semiconductor device includes channels for a pFET and an nFET. A SiGe layer is selectively grown in the source and drain regions of the pFET channel and a Si:C layer is selectively grown in source and drain regions of the nFET channel. The SiGe and Si:C layer match a lattice network of the underlying Si layer to create a stress component. In one implementation, this causes a compressive component in the pFET channel and a tensile component in the nFET channel.

Abstract translation: 一种半导体器件和制造半导体器件的方法。 该半导体器件包括用于pFET和nFET的沟道。 SiGe层选择性地生长在pFET沟道的源极和漏极区中，并且Si：C层选择性生长在nFET沟道的源极和漏极区中。 SiGe和Si：C层匹配下面的Si层的晶格网络以产生应力分量。 在一个实施方式中，这导致pFET沟道中的压缩分量和nFET沟道中的拉伸分量。

公开(公告)号：WO2005067677A2

公开(公告)日：2005-07-28

申请号：PCT/US2005000072

申请日：2005-01-04

Applicant: IBM

Inventor： BEDELL STEPHEN W ,  CHAN KEVIN K ,  CHIDAMBARRAO DURESETI ,  CHRISTIANSEN SILKE H ,  CHU JACK O ,  DOMENICUCCI ANTHONY G ,  LEE KAM-LEUNG ,  MOCUTA ANDA C ,  OTT JOHN A ,  OUYANG QIQING C

IPC: H01L21/336 ,  H01L21/84 ,  H01L27/01 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795

Abstract: A strained Fin Field Effect Transistor (FinFET) (and method for forming the same) includes a relaxed first material having a sidewall, and a strained second material formed on the sidewall of the first material. The relaxed first material and the strained second material form a fin of the FinFET.

Abstract translation: 应变Fin场效应晶体管（FinFET）（及其形成方法）包括具有侧壁的松弛的第一材料和形成在第一材料的侧壁上的应变的第二材料。 松弛的第一材料和应变的第二材料形成FinFET的鳍。

公开(公告)号：DE112012000310T5

公开(公告)日：2013-09-26

申请号：DE112012000310

申请日：2012-01-10

Applicant: IBM

Inventor： SLEIGHT JEFFREY W ,  TEKLEAB DANIEL G ,  HUNG TRAN H ,  CHIDAMBARRAO DURESETI

IPC: H01L29/78 ,  H01L21/336

Abstract: Eine nanoröhrenförmige MOSFET-Einheit und ein Verfahren zur Herstellung derselben werden verwendet, um den Leitplan für die Skalierung von Einheiten zu erweitern, während gute Kurzkanaleffekte aufrechterhalten werden und ein konkurrenzfähiger Treiberstrom bereitgestellt wird. Die nanoröhrenförmige MOSFET-Einheit beinhaltet ein konzentrisches röhrenförmiges inneres (61) und äußeres Gate (50), die durch eine röhrenförmig gestaltete, epitaxial aufgewachsene Siliciumschicht voneinander getrennt sind, sowie eine Source (35) beziehungsweise einen Drain (31), die durch Abstandshalter (511, 41) getrennt sind, welche das ringförmige innere und das ringförmige äußere Gate umgeben. Das Verfahren zum Bilden der nanoröhrenförmigen MOSFET-Einheit beinhaltet: Bilden einer zylindrisch geformten Si-Schicht (30) auf einem Substrat; Bilden eines äußeren Gates, das die zylindrische Si-Schicht (30) umgibt und zwischen einem unteren Abstandshalter (41) und einem oberen Abstandshalter (51) angeordnet ist; Aufwachsen einer epitaxialen Siliciumschicht auf dem oberen Abstandshalter angrenzend an einen Teil der zylindrisch geformten Si-Schicht; Ätzen eines inneren Teils des zylindrisch geformten Si, wobei ein hohler Zylinder gebildet wird; Bilden eines inneren Abstandshalters an dem Boden des inneren Zylinders; Bilden eines inneren Gates mittels Füllen eines Teils des hohlen Zylinders; Bilden eines Seitenwandabstandshalters angrenzend an das innere Gate; und Ätzen eines tiefen Grabens für ein Zugreifen auf das äußere Gate und den Drain sowie ein Kontaktieren derselben.