公开(公告)号：JP2006191029A

公开(公告)日：2006-07-20

申请号：JP2005363874

申请日：2005-12-16

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： DE SOUZA JOEL P ,  OTT JOHN A ,  REZNICEK ALEXANDER ,  SADANA DEVENDRA K ,  SAENGER KATHERINE L

IPC: H01L21/02

CPC classification number: H01L21/187 ,  H01L21/76251

Abstract: PROBLEM TO BE SOLVED: To provide a method of forming a bonding interface between Si having characteristics equal to that attained by hydrophobic bonding by removing an ultra thin interface oxide remaining after hydrophobic wafer bonding between Si.
SOLUTION: The interface oxide layer in the order of about 2-3 nm is dissolved and removed by, for example, high temperature annealing at 1,300-1,330°C only for 1-5 hours. The invention is most effectively used if the Si surface of a bonding interface has a different surface orientation as, for example, the Si surface with (100) orientation is bonded to the Si surface with (110) orientation. In more generous modes of this invention, an undesired material arranged on the bonding interface of two silicon-contained semiconductor materials can be removed by a similar annealing process. The surface crystal orientation, fine structure (single crystal, polycrystal, or amorphous), and elements of two silicon-contained semiconductor materials may or may not be identical.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供通过除去Si之间的疏水性晶片接合之后残留的超薄界面氧化物，形成具有与通过疏水接合获得的特性相同的特性的Si之间的结合界面的方法。 解决方案：通过例如1300-133℃的高温退火将约2-3nm量级的界面氧化物层溶解并除去1-5小时。 如果接合界面的Si表面具有不同的表面取向，则本发明是最有效的，因为例如具有（110）取向的具有（100）取向的Si表面结合到Si表面。 在本发明的更宽泛的模式中，可以通过类似的退火工艺去除布置在两个含硅半导体材料的结合界面上的不需要的材料。 表面晶体取向，精细结构（单晶，多晶或非晶）和两个含硅半导体材料的元素可以相同也可以不相同。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：WO2005067677A2

公开(公告)日：2005-07-28

申请号：PCT/US2005000072

申请日：2005-01-04

Applicant: IBM

Inventor： BEDELL STEPHEN W ,  CHAN KEVIN K ,  CHIDAMBARRAO DURESETI ,  CHRISTIANSEN SILKE H ,  CHU JACK O ,  DOMENICUCCI ANTHONY G ,  LEE KAM-LEUNG ,  MOCUTA ANDA C ,  OTT JOHN A ,  OUYANG QIQING C

IPC: H01L21/336 ,  H01L21/84 ,  H01L27/01 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795

Abstract: A strained Fin Field Effect Transistor (FinFET) (and method for forming the same) includes a relaxed first material having a sidewall, and a strained second material formed on the sidewall of the first material. The relaxed first material and the strained second material form a fin of the FinFET.

Abstract translation: 应变Fin场效应晶体管（FinFET）（及其形成方法）包括具有侧壁的松弛的第一材料和形成在第一材料的侧壁上的应变的第二材料。 松弛的第一材料和应变的第二材料形成FinFET的鳍。

公开(公告)号：WO2005057631A2

公开(公告)日：2005-06-23

申请号：PCT/US2004039970

申请日：2004-11-30

Applicant: IBM ,  DE SOUZA JOEL P ,  OTT JOHN A ,  REZNICEK ALEXANDER ,  SAENGER KATHERINE L

Inventor： DE SOUZA JOEL P ,  OTT JOHN A ,  REZNICEK ALEXANDER ,  SAENGER KATHERINE L

IPC: H01L21/20 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L29/04 ,  H01L29/10 ,  H01L29/786 ,  H01L21/00

CPC classification number: H01L29/78696 ,  H01L21/2022 ,  H01L21/76251 ,  H01L21/76275 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/045 ,  H01L29/1054 ,  H01L29/66772 ,  H01L29/78654

Abstract: A method utilizing localized amorphization and recrystallization of stacked template layers is provided for making a planar substrate having semiconductor layers of different crystallographic orientations. Also provided are hybrid­-orientation semiconductor substrate structures built with the methods of the invention, as well as such structures integrated with various CMOS circuits comprising at least two semiconductor devices disposed on different surface orientations for enhanced device performance.

Abstract translation: 提供了利用层叠模板层的局部非晶化和重结晶的方法，用于制造具有不同晶体取向的半导体层的平面基板。 还提供了利用本发明的方法构建的混合取向半导体衬底结构，以及与各种CMOS电路集成的这种结构，其包括设置在不同表面取向上的至少两个半导体器件，用于增强器件性能。

公开(公告)号：JP2003109918A

公开(公告)日：2003-04-11

申请号：JP2001300046

申请日：2001-09-28

Applicant: IBM

Inventor： CANAPERI DONALD F ,  COHEN GUY ,  RYAN HAN ,  OTT JOHN A ,  LOFARO MICHAEL ,  CHU JACK O

IPC: B24B37/00 ,  C08J5/14 ,  C09K3/14 ,  H01L21/304

Abstract: PROBLEM TO BE SOLVED: To provide a method and device by which a semiconductor substrate, a CMP tool, a brush cleaning tool, and a chemical wafer cleaning tool can be incorporated. SOLUTION: CMP is performed with a descending force of 1 psi, backward air pressure of 0.5 psi, platen speed of 50 rpm, carrier speed of 30 rpm, and slurry flow rate of 140 milliliter.

公开(公告)号：JP2000286413A

公开(公告)日：2000-10-13

申请号：JP2000065262

申请日：2000-03-09

Applicant: IBM

Inventor： CHU JACK OON ,  HAMMOND RICHARD ,  ISMAIL KHALID EZZELDIN ,  KOESTER STEVEN JOHN ,  MOONEY PATRICIA MAY ,  OTT JOHN A

IPC: H01L29/161 ,  H01L21/338 ,  H01L29/10 ,  H01L29/778 ,  H01L29/78 ,  H01L29/812

Abstract: PROBLEM TO BE SOLVED: To make applicable the structure of an epitaxial field effect transistor to the intended uses of high-speed low-noise microwave and quasi-millimetric- wave devices, etc., by integrating into the epitaxial field effect transistor a silicon layer, a germanium layer, and silicon-germanium layers which form jointly a modulatorily doped heterostructure. SOLUTION: After forming on a single-crystal semiconductor substrate 11 a buffer layer 12 including a layer 12A, a layer 12B, and a layer 12C, a p-type doped relaxation silicon-germanium layer 13 is formed on the layer 12C of the buffer layer 12. Then, thereon, as a spacer, a non-doped strained silicon layer 14 is grown epitaxially to grow further on the layer 14 epitaxially a non-doped thin relaxation silicon-germanium layer 15. Subsequently, on the layer 15, there are grown epitaxially in succession a germanium layer 16, a silicon-germanium layer 17, and a silicon-germanium cap layer 18 to form the laminated layer of them.

公开(公告)号：DE10011054A1

公开(公告)日：2000-09-21

申请号：DE10011054

申请日：2000-03-07

Applicant: IBM

Inventor： CHU JACK OON ,  HAMMOND RICHARD ,  ISMAIL KHALID EZZELDIN ,  KOESTER STEVEN JOHN ,  MOONEY PATRICIA MAY ,  OTT JOHN A

IPC: H01L29/161 ,  H01L21/338 ,  H01L29/10 ,  H01L29/778 ,  H01L29/78 ,  H01L29/812 ,  H01L21/335

Abstract: Layer structure arrangement comprises a single crystalline substrate, a first layer of relaxed Si1-xGex (where x = 0.35-0.5), a second layer of Si1-x, a third layer of non-doped silicon, a forth layer of non-doped Si1-x, a fifth layer of germanium, a sixth layer of Si1-wGew (where w = 0.5 to less than 1.0), and a seventh layer of Si1-xGex.

公开(公告)号：DE102014116231A1

公开(公告)日：2015-06-25

申请号：DE102014116231

申请日：2014-11-07

Applicant: IBM

Inventor： BAYRAM CAN ,  BEDELL STEPHEN W ,  FOGEL KEITH E ,  OTT JOHN A ,  SADANA DEVENDRA K

IPC: H01L21/20 ,  H01L33/30

Abstract: Eine Abspalt-Ablösungsebene wird in eine Gruppe-III-Nitrid-Materialschicht eingebettet gebildet. Die Abspalt-Ablösungsebene umfasst ein Material, welches eine andere Spannung, eine andere Struktur und eine andere Zusammensetzung als die Abschnitte der Gruppe-III-Nitrid-Materialschicht aufweist, welche die Gruppe-III-Nitrid-Materialschicht bereitstellen und die Abspalt-Ablösungsebene einbetten. Die Abspalt-Ablösungsebene stellt eine Region einer geschwächten Materialebene innerhalb der Gruppe-III-Nitrid-Materialschicht bereit, welche während eines anschließend durchgeführten Abspaltverfahrens verwendet werden kann, um einen der Abschnitte des Gruppe-III-Nitridmaterials von der ursprünglichen Gruppe-III-Nitrid-Materialschicht abzulösen. Speziell tritt während des Abspaltverfahrens innerhalb der Abspalt-Ablösungsebene, die in die ursprüngliche Gruppe-III-Nitrid-Materialschicht eingebettet ist, ein Beginn und eine Fortpflanzung von Rissen auf.

公开(公告)号：CA2871871A1

公开(公告)日：2015-06-19

申请号：CA2871871

申请日：2014-11-19

Applicant: IBM

Inventor： BAYRAM CAN ,  SADANA DEVENDRA ,  BEDELL STEPHEN W ,  OTT JOHN A ,  FOGEL KEITH E

IPC: H01L21/02 ,  H01L31/18 ,  H01L33/32

Abstract: A spall releasing plane is formed embedded within a Group III nitride material layer. The spall releasing plane includes a material that has a different strain, a different structure and a different composition compared with the Group III nitride material portions that provide the Group III nitride material layer and embed the spall releasing plane. The spall releasing plane provides a weakened material plane region within the Group III nitride material layer which during a subsequently performed spalling process can be used to release one of the portions of Group III nitride material from the original Group III nitride material layer. In particular, during the spalling process crack initiation and propagation occurs within the spall releasing plane embedded within the original Group III nitride material layer.