公开(公告)号：JP2000269441A

公开(公告)日：2000-09-29

申请号：JP29109099

申请日：1999-10-13

Applicant: IBM ,  SIEMENS AG

Inventor： JOACHIM HANS-OLIVER ,  MANDELMAN JACK A ,  RENGARAJAN RAJESH

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To reduce a swing below a threshold, a photoelectron degradation, and the sensitivity to a charge existing near the side wall of a device or the like, by forming a second divot shallower than a first divot in a region adjacent to an insulating P well. SOLUTION: This is a buried channel PFET device having a first deep divot 13 on the right side and a second shallow divot 12 on the left side. There is a gate conductor 14 of an N + polysilicon gate conductor and a p-type depletion layer 15 on an N well 11 surrounded by a nitride layer 16. A gate oxide layer 18 separates the gate conductor 14 from the depletion region 15. The nitride layer 16 contacts a shallow trench separation region 10. Contrary to an effect to a surface channel NFET, a parasitic conductance at the edge is produced by the shallow divot 12 in the buried channel PFET. If a gate control is out of control, a gradient below a threshold, an off current, and the reliability of a photoelectron are reduced.

公开(公告)号：JP2000252445A

公开(公告)日：2000-09-14

申请号：JP2000046447

申请日：2000-02-23

Applicant: IBM

Inventor： RAMACHANDRA DIVAKARUUNI ,  EUGENE LEE ,  MANDELMAN JACK A

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8242 ,  H01L27/00 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a method and structure for generating more stable threshold voltage. SOLUTION: Related to the integrated circuit element and manufacture of it, a gate stack is formed wherein a pattern comprising a storage node diffusion region adjacent to a storage element and a bit line conduct diffusion region 306 facing the storage node diffusion region is formed. An impurity is implanted in the storage node diffusion region and bit line contact diffusion region 306 and an insulator layer is formed on the gate stack with the pattern. A side wall spacer is formed along a part of the gate stack with a pattern adjoining the bit line contact diffusion region 306, and a halo implant 60 is implanted in the bit line contact diffusion region so that no insulator layer blocks the halo implant from the second diffusion region. Further, the integrated circuit element is annealed so that the halo implant 60 is diffused before the impurity is diffused.

公开(公告)号：JP2000228504A

公开(公告)日：2000-08-15

申请号：JP2000028340

申请日：2000-02-04

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： MANDELMAN JACK A ,  LAROSA GIUSEPPE ,  RADENS CARL ,  DIVAKARUNI RAMA ,  GRUENING ULRIKE

IPC: H01L21/76 ,  H01L21/763 ,  H01L21/765 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a dynamic random access memory formed at a semiconductor body comprising individual paired memory cell separated each other by a vertical electric isolation trench and separated from a support circuit. SOLUTION: An isolation trench 20, comprising a side wall, upper part, and lower part, encloses the region of a semiconductor body 10 comprising a memory cell. Thus, the paired memory cell is electrically separated each other, while separated from a support circuit which is not in the enclosed region but contained in the semiconductor body. The isolation trench lower-part is filled with a conductive material 14, which material comprises a side wall part which is at least partially separated from the trench lower-part side wall by a first electric insulator and a lower part electrically connecting to the semiconductor body. The isolation trench upper-part is filled with a second electric insulator.

公开(公告)号：JPH11274478A

公开(公告)日：1999-10-08

申请号：JP2893699

申请日：1999-02-05

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレイション

Inventor： FURUKAWA TOSHIHARU ,  MARK C HAKEY ,  STEPHEN J HORMES ,  DAVID V HOLLACK ,  WILLIAM H MA ,  MANDELMAN JACK A

IPC: H01L21/225 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L29/66613 ,  H01L21/2255 ,  H01L29/66621 ,  H01L29/7834

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor element reducing a short channel effect. SOLUTION: An element has a trench 370 formed in a silicon substrate 305. The channel 380 of the element is formed on the bottom portion of the trench 370. Diffusion layers 310, 320 are formed adjacently to both sides of the trench 370 and are extended along the side walls of the trench 370 and under a part of the trench 370 to form diffusion extension parts 315, 325, whereby each diffusion layer is connected to each edge of the element channel.

Abstract translation: 要解决的问题：提供减少短通道效应的半导体元件。 解决方案：元件具有形成在硅衬底305中的沟槽370.元件的沟道380形成在沟槽370的底部上。扩散层310,320形成在沟槽370的两侧相邻并且延伸 沿着沟槽370的侧壁并在沟槽370的一部分之下形成扩散延伸部分315,325，由此每个扩散层连接到元件沟道的每个边缘。

公开(公告)号：JPH1117001A

公开(公告)日：1999-01-22

申请号：JP16022198

申请日：1998-06-09

Applicant: IBM

Inventor： MARK A JEISO ,  MANDELMAN JACK A ,  TONTI WILLIAM R ,  WORDEMAN MATTHEW R

IPC: H01L21/20 ,  H01L21/76 ,  H01L21/762 ,  H01L21/84 ,  H01L27/12

Abstract: PROBLEM TO BE SOLVED: To provide an SOI(silicon on Insulator)/bulk hybrid semiconductor substrate. SOLUTION: A semiconductor device has SOI regions 120 and bulk regions 122. In single crystal semiconductor regions, conductive spacers 124 are provided to electrically connect the SOI regions to the ground, thereby overcoming the floating body effect. Insulative spacers 126 are formed on the conductive spacers 124 to electrically separate the SOI regions 120 from the bulk regions 122. In manufacturing process of these regions, a sacrificial polishing layer is deposited to the epitaxially grown single crystal bulk regions, and there is no need to selectively grow.

公开(公告)号：JP2007123893A

公开(公告)日：2007-05-17

申请号：JP2006290462

申请日：2006-10-25

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： MANDELMAN JACK A ,  CHENG KANGGUO

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10841 ,  G11C11/403 ,  G11C11/405 ,  H01L27/0207 ,  H01L27/10864 ,  H01L27/10894 ,  H01L29/045

Abstract: PROBLEM TO BE SOLVED: To provide improved gain and cell and a method for manufacturing and using the same. SOLUTION: In a first embodiment, the memory cell of a substrate containing (1) a PFET having almost planar orientation to the surface of the substrate and (2) an NFET coupled to an almost planar PFET is provided. The orientation of the NFET inside the substrate is almost vertical to that of the PFET. The invention includes many other embodiments. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供改进的增益和电池及其制造和使用方法。 解决方案：在第一实施例中，提供了一种衬底的存储单元，其包含（1）具有与衬底表面几乎平面取向的PFET和（2）耦合到几乎平面的PFET的NFET。 衬底内部NFET的取向几乎与PFET垂直。 本发明包括许多其它实施例。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2004015053A

公开(公告)日：2004-01-15

申请号：JP2003151411

申请日：2003-05-28

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： MANDELMAN JACK A ,  HO HERBERT L

IPC: H01L21/334 ,  H01L21/8242 ,  H01L21/84 ,  H01L27/108 ,  H01L27/12 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC classification number: H01L27/10867 ,  H01L21/84 ,  H01L27/10829 ,  H01L27/1203 ,  H01L29/66181

Abstract: PROBLEM TO BE SOLVED: To increase the degree of vertical separation between a passing wordline and a strap.
SOLUTION: If the thickness of an insulation layer is decreased in an SOI integrated circuit including a trench capacitor DRAM array, crosstalk is caused between a trench capacitor and the passing wordline 214 which passes over the trench capacitor. The buried strap on a capacitor center electrode 105 is enabled to come into contact with the backside of an SOI layer 60 by increasing the depth of a recess at the upper part of the trench and laterally undercutting the insulating layer, thereby increasing the degree of vertical separation between the passing wordline 214 and the strap.
COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2002305287A

公开(公告)日：2002-10-18

申请号：JP2002016927

申请日：2002-01-25

Applicant: IBM

Inventor： MANDELMAN JACK A ,  RADENS CARL J

IPC: H01L27/108 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/092 ,  H01L27/10 ,  H01L29/423 ,  H01L29/43 ,  H01L29/49

Abstract: PROBLEM TO BE SOLVED: To provide a complementary metal-oxide film semiconductor integrated circuit which contains a notched gate in a support device region, and to provide a method of forming the integrated circuit. SOLUTION: A gate stack 16 is formed on a substrate, a patterned mask 24 is formed on the gate stack, the stack gate is etched by using the mask, and rather than the entire part but a part of a gate conductor is removed. A gap-filling film 28 is formed on the whole face, and the gap-filling film is removed in such a way that the gap filling film is left between masked gate stacks in an array device region. A spacer is formed on the exposed sidewall of the masked gate stack, and the exposed gate conductor inside the array device region and inside the support device region is removed. An undercut is formed in the lower exposed part of the remaining gate conductor. The remaining gap filling film is removed from the masked protective gate stack inside the array device region.

公开(公告)号：JP2002222873A

公开(公告)日：2002-08-09

申请号：JP2001388866

申请日：2001-12-21

Applicant: IBM

Inventor： RAMACHANDORA DEIVAKARUNI ,  LEE HEON ,  MANDELMAN JACK A ,  RADENS CARL J ,  SIM JAI-HOON

IPC: H01L21/8242 ,  H01L21/336 ,  H01L27/108 ,  H01L29/772

Abstract: PROBLEM TO BE SOLVED: To provide an improved method of forming a vertical MOSFET structure. SOLUTION: A method of forming a semiconductor memory cell array structure comprises a process of providing a vertical MOSFET DRAM cell structure having a deposited gate conductor layer 22 planarized up to the top surface of a trench top oxide 24 on a silicon substrate, a process of forming a recess 39 in the gate conductor layer below the top surface of the silicon substrate, a process of forming doping pockets 46 in an array P well 32 by implanting N-type dopant species through the recess at an angle, a process of forming spacers 44 on the side wall of the recess by depositing an oxide layer in the recess and then etching the oxide layer, and a process of depositing a gate conductor material in the recess and then planarizing the gate conductor material up to the top surface of the trench top oxide.

公开(公告)号：JP2001345383A

公开(公告)日：2001-12-14

申请号：JP2001160548

申请日：2001-05-29

Applicant: IBM

Inventor： CLAUDEL L BARTIN ,  RAMACHANDORA DEIVAKARUNI ,  HOUGHTON RUSSELL J ,  MANDELMAN JACK A ,  TONTI WILLIAM R

IPC: H01L21/82 ,  H01L21/334 ,  H01L23/525 ,  H01L27/108 ,  H01L27/12

Abstract: PROBLEM TO BE SOLVED: To provide an anti-fuse structure which can program at a low voltage and current, uses only in an extremely small chip base, and can be formed in a gap between parts which are disposed at intervals of a least lithographic feature size. SOLUTION: An anti-fuse structure is formed on an SOI substrate in combination with a capacitor-like structure which reaches support layer or in the support layer by etching a contact which penetrates an insulator and reaches the support semiconductor layer. This anti-fuse can be programmed by selecting a position forming a conductor or damaging a dielectric of the capacitor-like structure. It is possible to restrict the damages to a desirable position by use of an insulation collar enclosing the conductor or a part of the capacitor-like structure. Thermal influences due to a programming current are isolated into the interior of a bulk silicon layer, whereby a programming during a normal operation of a device is enabled.