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    54.
    发明专利
    未知

    公开(公告)号：DE10120672C2

    公开(公告)日：2003-03-20

    申请号：DE10120672

    申请日：2001-04-27

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： FISCHER HELMUT ,  CHRISSOSTOMIDIS IOANNIS

    IPC: G11C7/10 ,  G11C11/412

    Abstract: Data register for storage of a data bit with integrated signal level conversion. The data register has an input for application of a data bit input signal which has a first voltage shift between a reference ground potential and a first voltage potential, a controllable switching device for passing on the applied data bit signal, a potential isolating transistor having a control connection at the first voltage potential, a first inverter which emits, in inverted form, the passed-on data bit input signal as a data bit output signal having a second voltage shift between the reference ground potential and a second supply potential, at one output of the data register for further data processing, and a second inverter, which feeds back the data output signal for storage of the data bit.

    55.
    发明专利
    未知

    公开(公告)号：DE10139515A1

    公开(公告)日：2003-03-06

    申请号：DE10139515

    申请日：2001-08-10

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： FISCHER HELMUT ,  LINDOLF JUERGEN

    IPC: G05F3/30 ,  H01L29/732 ,  H01L29/73 ,  H01L23/58 ,  G05F3/22

    Abstract: A transistor configuration for a bandgap circuit is configured in the form of an npn transistor. An insulated p-type well, which is surrounded by a buried n-type well, is used as a base terminal. The n-type well constitutes the emitter terminal. A negatively doped region, which acts as a collector terminal, is formed in the p-type well. The structure that is used exists in DRAM processes, and it can therefore be used to form an npn transistor as a footprint diode in bandgap circuits.

    56.
    发明专利
    未知

    公开(公告)号：DE10130978A1

    公开(公告)日：2003-01-16

    申请号：DE10130978

    申请日：2001-06-27

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： FISCHER HELMUT ,  ZIMMERMANN ELLEN

    IPC: G11C29/00

    Abstract: A RAM circuit has a memory cell array whose number of rows is an integer multiple of an integer p>1 and is composed of regular and redundant rows. Each row is assigned a driver. The space occupied by the cell array and by the drivers is subdivided into two sections, in each of which there is situated a subset of the regular rows and a subset of the redundant rows. In the first section, the number of rows is by a number k smaller than an integer multiple of p. In each section, each driver occupies a location allocated to it in a regular two-dimensional pattern of locations, each of which has one of p possible X coordinates in the row direction. The locations of the pattern are occupied without any vacancies within the first section, and, within the second section, p-k locations of the pattern are unoccupied.

    57.
    发明专利
    未知

    公开(公告)号：DE10121837C1

    公开(公告)日：2002-12-05

    申请号：DE10121837

    申请日：2001-05-04

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： FISCHER HELMUT ,  PFEIFFER JOHANN

    IPC: G11C7/06 ,  G11C7/10 ,  G11C7/12 ,  G11C8/12 ,  G11C11/4094 ,  G11C11/4096

    Abstract: A memory circuit has at least two memory areas each including a group of primary read amplifiers. Each of these groups can be connected via an assigned local two-conductor data line to a two-conductor master data line whose conductors are connected to the input terminals of a secondary read amplifier. Before switching through a connection from a primary read amplifier to the secondary read amplifier, each of the conductors in both the relevant local data line and the master data line are equalized to a potential lying between two logic potentials. The supply potentials of the secondary read amplifier are provided so that the secondary read amplifier operates within the amplifying operating range when either of its input terminals is driven to the first logic potential and the other input terminal is driven to the second logic potential.

    59.
    发明专利
    未知

    公开(公告)号：DE10051613A1

    公开(公告)日：2002-05-02

    申请号：DE10051613

    申请日：2000-10-18

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： FISCHER HELMUT ,  CHRISSOSTOMIDIS IOANNIS ,  SCHAFFROTH THILO

    IPC: G11C7/06 ,  G11C7/08 ,  G11C7/22 ,  G11C11/4091 ,  G11C5/14

    Abstract: The circuit has a first current path for activation of the memory via an addressed word line, a second current path in which a read amplifier control signal is generated by a controler from a signal (RAVLD) derived from the first current path and a voltage supply device for components of the two current paths. Thick oxide transistors (T) supplied with an increased supply voltage are provided in the second path in addition to thin oxide transistors (T') supplied with a normal voltage.

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