公开(公告)号：DE10248722A1

公开(公告)日：2004-05-06

申请号：DE10248722

申请日：2002-10-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ROESNER WOLFGANG ,  SCHULZ THOMAS ,  HARTWICH JESSICA ,  BREDERLOW RALF ,  PACHA CHRISTIAN

IPC: H01L21/336 ,  H01L21/8242 ,  H01L21/84 ,  H01L27/06 ,  H01L27/108 ,  H01L27/12 ,  H01L29/786

Abstract: Integrated switching arrangement comprises an electrically insulating region, an electrode region close to the insulating region, and an electrode region away from the insulating region. The insulating region is a component of an insulating layer arranged in one surface. A capacitor (124) and an active component (122) of the switching arrangement are arranged on the same side of the insulating layer. The electrode region close to the insulating region and the active region of the component are arranged in one surface which lies parallel to the surface in which the insulating layer is arranged. An independent claim is also included for a process for the production of an integrated switching arrangement.

公开(公告)号：DE10241173A1

公开(公告)日：2004-03-11

申请号：DE10241173

申请日：2002-09-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHULZ THOMAS ,  HOFMANN FRANZ ,  SPECHT MICHAEL ,  LANDGRAF ERHARD ,  LYKEN R JOHANNES

IPC: H01L21/20 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/115 ,  H01L29/73 ,  H01L29/76 ,  H01L29/792

Abstract: The invention relates to a semiconductor memory having a multiplicity of memory cells, each of the memory cells having N (e.g., four) vertical memory transistors with trapping layers. Higher contact regions are formed in higher semiconductor regions extending obliquely with respect to the rows and columns of the cell array, the gate electrode generally being led to the step side areas of the higher semiconductor region. A storage density of 1-2F 2 per bit can thus be achieved.

公开(公告)号：DE10118405A1

公开(公告)日：2002-10-24

申请号：DE10118405

申请日：2001-04-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LUYKEN JOHANNES R ,  ROESNER WOLFGANG ,  HOFMANN FRANZ ,  SCHULZ THOMAS

IPC: B82B1/00 ,  A61K48/00 ,  G01Q70/08 ,  G01Q70/12 ,  H01L29/06 ,  H01L29/15 ,  H01L29/16 ,  H01L29/20 ,  H01L29/26 ,  H01L29/267 ,  H01L29/86 ,  H01L51/05 ,  H01L51/30 ,  B81C1/00 ,  B81C3/00 ,  H01L51/20

Abstract: Heterostructure component comprises a single hetero-nanotube (110) having a first region (101) made from a nanotube material having a first energy band gap value and a second region (102) made from a nanotube material having a second energy band gap value which is different from the first value. The second region is arranged on the upper end (103) of the first region in the longitudinal direction of the hetero-nanotube. An Independent claim is also included for a process for the production of the heterostructure component. Preferred Features: The hetero-nanotube has a further region made from a material having a further different energy band gap value.

公开(公告)号：DE19746900C2

公开(公告)日：2002-02-14

申请号：DE19746900

申请日：1997-10-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHULZ THOMAS ,  AEUGLE THOMAS ,  ROESNER WOLFGANG

IPC: H01L29/41 ,  H01L21/336 ,  H01L29/78

Abstract: A first part (S/D1a) of a first source/drain region (S/D1) is disposed on at least one flank of a semiconductor structure (St) and on at least one peripheral region of a surface (OH), bordering the flank, of the semiconductor structure (St). A dimension of the first part (S/D1a) of the first source/drain region (S/D1) perpendicular to the flank is less than an analogous dimension of the semiconductor structure (St) and than the minimum feature size that can be made by the technology used. For the production, a mask that is used to create the semiconductor structure (St) can be reduced in size for the implantation of the first part (S/D1a) of the first source/drain region (S/D1). To make it easier to create a contact (K1) of the first source/drain region (S/D1), a second part (S/D1b) of the first source/drain region (S/D1) can be disposed in an inner region of the surface (OH) of the semiconductor structure (St). A dimension of the second part (S/D1b) of the first source/drain region (S/D1) perpendicular to the surface (OH) of the semiconductor structure (St) is smaller than an analogous dimension of the first part (S/D1a) of the first source/drain region (S/D1).

公开(公告)号：DE19942692A1

公开(公告)日：2001-04-12

申请号：DE19942692

申请日：1999-09-07

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHULZ THOMAS ,  ROESNER WOLFGANG ,  RISCH LOTHAR

IPC: H01L27/14 ,  H01L27/144 ,  H01L27/15 ,  H01L31/0232 ,  H01L31/10 ,  H01L31/102 ,  G02B6/42

Abstract: In an integrated optoelectronic microelectronic system, an optoelectronically active diode part is formed in a semiconductor substrate by zones forming depletion layers. The system is provided in a mesa that stands vertically on a semiconductor substrate and runs in a direction of extension thereof. A light waveguide is optically coupled to the diode part in such a way that light is coupled into the diode part via the mesa side wall.

公开(公告)号：DE102007054058B4

公开(公告)日：2014-10-16

申请号：DE102007054058

申请日：2007-11-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOSSNER HARALD ,  RUSS CHRISTIAN ,  SCHNEIDER JENS ,  SCHULZ THOMAS

IPC: H01L29/78 ,  H01L21/336 ,  H01L23/367

Abstract: Halbleiter (10), umfassend: – eine Source-Zone (16); – eine Drain-Zone (12); – eine Anordnung von Finnen (18), die mit einer Gate-Zone (22) operativ gekoppelt sind, welche dazu ausgebildet ist, den Stromfluss durch die Finnen (18) zwischen der Source-Zone (16) und der Drain-Zone (12) zu steuern, und – mindestens ein Kühlelement (30; 40), das wenigstens zum Teil aus einem Material geformt ist, das eine Wärmekapazität hat, die größer ist als die Wärmekapazität des Materials der Source-Zone, der Drain-Zone und der Anordnung von Finnen, wobei das Kühlelement sich in nächster Nähe zu den Finnen (18) der Firmenanordnung befindet und von den Finnen (18), der Source-Zone (16), der Drain-Zone (12) und der Gate-Zone (22) elektrisch isoliert ist und wobei das mindestens eine Kühlelement (30; 40) ein Balken- bzw. Stabkontakt (30; 40) ist, der sich quer zu und oberhalb von wenigstens zwei Firmen (18) der Finnenanordnung befindet.

公开(公告)号：DE10211337B4

公开(公告)日：2009-12-31

申请号：DE10211337

申请日：2002-03-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PACHA CHRISTIAN ,  SCHULZ THOMAS

IPC: G11C14/00 ,  G11C11/41 ,  G11C11/419

公开(公告)号：DE102008001208A1

公开(公告)日：2009-02-19

申请号：DE102008001208

申请日：2008-04-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHULZ THOMAS

IPC: H01L31/0232 ,  G02B6/42 ,  H01L31/10

Abstract: One embodiment provides an integrated circuit including a first non-planar structure and a waveguide configured to provide electromagnetic waves to the first non-planar structure. The first non-planar structure provides a first signal in response to at least some of the electromagnetic waves.

公开(公告)号：DE102008001209A1

公开(公告)日：2008-12-18

申请号：DE102008001209

申请日：2008-04-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHULZ THOMAS

IPC: H01L21/336 ,  H01L29/49 ,  H01L29/78

公开(公告)号：DE112006003059T5

公开(公告)日：2008-10-09

申请号：DE112006003059

申请日：2006-11-10

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LI HONG-JYH ,  SCHULZ THOMAS

IPC: H01L21/8238 ,  H01L21/336 ,  H01L21/84 ,  H01L27/12 ,  H01L29/49 ,  H01L29/786

Abstract: Semiconductor devices with transistors having different gate dielectric materials and methods of manufacture thereof are disclosed. One embodiment includes a semiconductor device including a workpiece, the workpiece including a first region and a second region proximate the first region. A first transistor is disposed in the first region of the workpiece, the first transistor having at least two first gate electrodes. A first gate dielectric is disposed proximate each of the at least two first gate electrodes, the first gate dielectric comprising a first material. A second transistor is disposed in the second region of the workpiece, the second transistor having at least two second gate electrodes. A second gate dielectric is disposed proximate each of the at least two second gate electrodes, the second gate dielectric comprising a second material. The second material is different than the first material.