52.
    发明专利
    未知

    公开(公告)号:DE69820594D1

    公开(公告)日:2004-01-29

    申请号:DE69820594

    申请日:1998-05-29

    Abstract: The reading method comprises the steps of: supplying simultaneously two memory cells (F1, F2), both storing a respective unknown charge condition; generating two electrical quantities (Va, Vb), each correlated to a respective charge condition; comparing the two electrical quantities (Va, Vb) with each other; and generating a two-bit signal (01, 02) on the basis of the result of the comparison. The reading circuit comprises a two-input comparator (58) comprising two branches in parallel, each branch being connected to a respective memory cell by a current/voltage converter (41). Both the two-input comparator (58) and the current/voltage converter (41) comprise low threshold transistors (49, 50, 65-68).

    54.
    发明专利
    未知

    公开(公告)号:IT1316002B1

    公开(公告)日:2003-03-26

    申请号:ITRM20000577

    申请日:2000-11-08

    Abstract: A voltage regulator having a comparator with an output terminal that is the output of the regulator, terminals for connection to a voltage supply, a source of a reference voltage connected to an input terminal of the comparator, and a feedback circuit connected between the output terminal and the other input terminal of the comparator. To prevent transients upon the transition from the standby state to the active state, there is provided a second reference-voltage source that provides a reference voltage substantially equal to that of the first source, a switch for connecting the second source to the other input terminal of the comparator, and a control circuit that can activate the supply of the regulator and can close the switch for a predetermined period of time when the supply of the regulator is activated.

    55.
    发明专利
    未知

    公开(公告)号:ITTO20000892A1

    公开(公告)日:2002-03-22

    申请号:ITTO20000892

    申请日:2000-09-22

    Abstract: Described herein is a nonvolatile memory comprising a memory array organized according to global word lines and local word lines; a global row decoder; a local row decoder; a first supply stage for supplying the global row decoder; and a second supply stage for supplying the local row decoder; and a third supply stage for biasing the drain and source terminals of the memory cells of the memory array. Each of the supply stages comprises a respective resistive divider formed by a plurality of series-connected resistors, and a plurality of pass-gate CMOS switches each connected in parallel to a respective resistor. The nonvolatile memory further comprises a control circuit for controlling the pass-gate CMOS switches of the supply stages, and a switching circuit for selectively connecting the supply input of the control circuit to the output of the second supply stage during reading and programming of the memory, and to the output of the third supply stage during erasing of the memory.

    56.
    发明专利
    未知

    公开(公告)号:IT1311441B1

    公开(公告)日:2002-03-12

    申请号:ITTO990994

    申请日:1999-11-16

    Abstract: The voltage generator comprises a negative feedback loop including a programmable voltage divider having a feedback node. The voltage divider comprises a programmable resistor disposed between the output of the voltage generator and the feedback node and having variable resistance. The programmable resistor includes a fixed resistor and a plurality of additional resistors arranged in series with each other and defining a plurality of intermediate nodes. The additional resistors may be selectively connected by means of switches disposed between the output of the voltage generator and a respective intermediate node so as to define an output voltage V0 programmable on the basis of command signals supplied to the switches.

    57.
    发明专利
    未知

    公开(公告)号:IT1311440B1

    公开(公告)日:2002-03-12

    申请号:ITTO990993

    申请日:1999-11-16

    Abstract: A voltage generator formed of a charge circuit and a discharge circuit having a common programmable voltage divider with variable resistance; the programmable voltage divider including a plurality of resistors arranged in series and selectively connectable to define alternatively a step-wise increasing program voltage and a fixed verify voltage. The charge circuit formed of a voltage regulator supplying at the output the precise voltage value determined by the programmable voltage divider, and the discharge circuit intervening when the output voltage must be switched in a controlled manner from a higher value to a lower value.

    59.
    发明专利
    未知

    公开(公告)号:ITTO990993A1

    公开(公告)日:2001-05-16

    申请号:ITTO990993

    申请日:1999-11-16

    Abstract: A voltage generator formed of a charge circuit and a discharge circuit having a common programmable voltage divider with variable resistance; the programmable voltage divider including a plurality of resistors arranged in series and selectively connectable to define alternatively a step-wise increasing program voltage and a fixed verify voltage. The charge circuit formed of a voltage regulator supplying at the output the precise voltage value determined by the programmable voltage divider, and the discharge circuit intervening when the output voltage must be switched in a controlled manner from a higher value to a lower value.

Patent Agency Ranking