Abstract:
An improved through-via vertical interconnect, through-via heat sinks and associated fabrication techniques are provided for. The devices benefit from an organic dielectric layer 18 that allows for low-temperature deposition processing. The low-temperature processing used to form the through-via interconnects and heat sinks allows for the formation of the interconnects and heat sinks at any point in the fabrication of the semiconductor device, including post-formation of active devices and associated circuitry. The through-via vertical interconnects of the present invention are fabricated so as to insure conformal thickness of the various layers that form the interconnect constructs. As such, the interconnects can be formed with a high aspect ratio, in the range of about 4:1 to about 10:1, substrate thickness to interconnect diameter.
Abstract:
The present invention relates to a solder stop in through-plated through-holes in micro strip boards (8). A solder resist lacquer (18) with a certain viscosity is applied on a micro strip board (8) wherein the solder resist lacquer (18) flows out over the micro strip board (8) and down into a number of through-holes (14) before the solder resist lacquer is dried. A mask is placed over the dried solder resist lacquer (18), whereby transparent center surfaces on the mask are centered over respective openings in the through-holes (14). The micro strip board (8) is exposed to UV-light so that certain parts of the solder resist lacquer (18) on the micro strip board (8) and in the through-holes (14) are reached by the UV-light, whereby the exposed parts of the solder resist lacquer (18) can cure a first time. The micro strip board (8) is cleaned so that the parts of the solder resist lacquer (18) which have not cured are removed from the micro strip board (8). The micro strip board (8) is then placed in a heat oven, whereby the solder resist lacquer is cured completely by the heat in the oven a last time. The remaining completely cured solder resist lacquer has in this way formed a solder stop (61) in the respective through-hole (14).
Abstract:
An electrical connection between a transmission line and an integrated circuit package comprises, a circuit board (12) on which are mounted a transmission line (28, 402, 202, 503, 505) and an integrated circuit package (10), a projecting portion of a pin (14, 14A, 14B) projecting from an integrated circuit package (10), a transmission line feed (32, 404) that further comprises a waveguide cavity (204, 504, 506) connected to the pin (14, 14A, 14B) and a dielectric material (106) surrounding the pin (14, 14A, 14B), the dielectric material being between the pin and a ground feed (92, 412, 414, 208, 508, 510) of the transmission line (28, 402, 202, 503, 505).
Abstract:
개선된 관통 바이어형 수직 상호접속부, 관통 바이어형 열 싱크 및 이와 관련된 제작 기술이 제공된다. 이러한 장치들은 저온 증착 처리를 가능하게 하는 유기 유전층으로부터 이점을 얻는다. 관통 바이어형 상호접속부 및 열 싱크를 형성하기 위해 사용되는 저온 처리는 능동 소자 및 이와 관련된 회로 소자의 형성 이후를 포함하여, 반도체 장치의 제작의 임의의 시점에서 상호접속부 및 열 싱크의 형성을 가능하게 한다. 본 발명의 관통 바이어형 수직 상호접속부는 상호접속부 구성을 형성하는 다양한 층의 균일한 두께를 보장하도록 제작된다. 이에 따라, 상호접속부는 기판 두께 대 상호접속부 직경이 약 4:1 내지 약 10:1의 높은 종횡비를 갖도록 형성된다.
Abstract:
The method comprises providing a semiconductor substrate (1), which has a main surface (12) and an opposite further main surface (13), arranging a contact pad (19) above the further main surface, forming a through-substrate via (4) from the main surface to the further main surface at a distance from the contact pad and, by the same method step together with the through-substrate via, forming a further through- substrate via (14) above the contact pad, arranging a hollow metal via layer (5) in the through-substrate via and, by the same method step together with the metal via layer, arranging a further metal via layer (15) in the further through- substrate via, the further metal via layer contacting the contact pad, and removing a bottom portion of the metal via layer to form an optical via laterally surrounded by the metal via layer.