公开(公告)号：EP0513743B1

公开(公告)日：1997-09-10

申请号：EP92108008.1

申请日：1992-05-12

Applicant: FUJITSU LIMITED

Inventor： Michio, Sono, c/o Fujitsu Limited ,  Junichi, Kasai, c/o Fujitsu Limited ,  Masanori, Yoshimoto,c/o Fujitsu Limited ,  Kazuto, Tsuji, c/o Fujitsu Limited ,  Kouji, Saito, c/o Fujitsu Limited

IPC: H01L23/495

CPC classification number: H05K3/303 ,  H01L23/49555 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/181 ,  H05K3/3426 ,  H05K2201/09709 ,  H05K2201/09781 ,  H05K2201/10454 ,  H05K2201/10522 ,  H05K2201/10568 ,  H05K2201/10659 ,  H05K2201/10696 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/05599

公开(公告)号：EP0513743A2

公开(公告)日：1992-11-19

申请号：EP92108008.1

申请日：1992-05-12

Applicant: FUJITSU LIMITED

Inventor： Michio, Sono, c/o Fujitsu Limited ,  Junichi, Kasai, c/o Fujitsu Limited ,  Masanori, Yoshimoto,c/o Fujitsu Limited ,  Kazuto, Tsuji, c/o Fujitsu Limited ,  Kouji, Saito, c/o Fujitsu Limited

IPC: H01L23/495

CPC classification number: H05K3/303 ,  H01L23/49555 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/181 ,  H05K3/3426 ,  H05K2201/09709 ,  H05K2201/09781 ,  H05K2201/10454 ,  H05K2201/10522 ,  H05K2201/10568 ,  H05K2201/10659 ,  H05K2201/10696 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A semiconductor device (10) having a package (11) of a single in-line type comprises a semiconductor chip (15), a package body (11) that accommodates the semiconductor chip (15) therein and defined by a pair of opposing major surfaces (11a, 11b), a plurality of interconnection leads (14) held by the package body to extend substantially perpendicularly to a bottom surface (11 f ), wherein each of the interconnection leads consists of an inner lead part (14b) located inside the package body and an outer lead part (14a) located outside the package body, the outer lead part being bent laterally at a boundary between the inner part and outer part, in one of first and second directions that are opposite from each other and substantially perpendicular to the opposing major surfaces (11a, 11b) of the package body. The semiconductor device further includes a plurality of support legs (12a - 13b) extending laterally at the bottom surface (11 f ) of the package body for supporting the package body upright when the semiconductor device is placed on a substrate.

Abstract translation: 具有单列直插式封装的半导体器件包括半导体芯片（15），其中容纳半导体芯片并由一对相对的主表面（11a，11b）限定的封装体（11），多个 由所述封装主体保持的互连引线（14）基本上垂直于底表面（11f）延伸，其中每个所述互连引线由位于所述封装主体内部的内引线部分（14b）和外引线部分（14a） ），所述外引线部分在所述内部部分和外部部分之间的边界处侧向弯曲，所述外引线部分在第一和第二方向之一中彼此相对并且基本上垂直于相对的主表面（11a，11b） ）的包装体。 半导体器件还包括在封装主体的底表面（11f）处横向延伸的多个支撑腿（12a-13b），用于当将半导体器件放置在衬底上时支撑封装体直立。

公开(公告)号：EP0333374A3

公开(公告)日：1991-01-16

申请号：EP89302297.0

申请日：1989-03-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Baudouin, Daniel A. ,  Russell, Ernest J.

IPC: H05K3/30 ,  H01L23/50 ,  H01L23/495 ,  H01L23/04

CPC classification number: H05K3/303 ,  H01L23/49555 ,  H01L2924/0002 ,  H05K2201/10454 ,  H05K2201/10568 ,  H05K2201/10696 ,  H05K2203/167 ,  Y02P70/613 ,  H01L2924/00

Abstract: A flat package (10) for semiconductor integrated circuit devices allows edge-mounting and surface-mount. The package may be molded plastic (12) containing a semiconductor chip (11), and flat leads (14) extend from one edge of the package. The leads are bent to provide an area (18) to solder to conductors on a PC board. Mechanical positioning, mechanical support and spacing are provided by studs (15) extending from the edge of the package adjacent the leads. The studs have stops (17) formed at a position even with flat outer surfaces of the bent leads; the portion outward of the stops fits into holes in the PC board.

公开(公告)号：US07082681B2

公开(公告)日：2006-08-01

申请号：US10427518

申请日：2003-05-01

Applicant: Larry D. Kinsman ,  Walter L. Moden ,  Warren M. Farnworth

Inventor： Larry D. Kinsman ,  Walter L. Moden ,  Warren M. Farnworth

IPC: H05K3/30

CPC classification number: H05K3/301 ,  H01L25/105 ,  H01L2225/107 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K2201/10454 ,  H05K2201/10696 ,  Y10S83/942 ,  Y10T29/49121 ,  Y10T29/4913 ,  Y10T29/49135 ,  Y10T29/49147 ,  Y10T29/49156 ,  Y10T29/49169 ,  Y10T29/53174 ,  Y10T29/53178 ,  H01L2924/00

Abstract: A vertically mountable semiconductor device including a plurality of stub contacts extending perpendicularly from a bottom edge thereof. The stub contacts may be formed by trimming the leads of an existing vertical surface mount package. A complementary alignment device includes a receptacle for receiving the vertically mountable semiconductor device. The alignment device is attachable to a carrier substrate. Upon attachment of the alignment device to a carrier substrate and insertion of a vertically mountable semiconductor device into the receptacle, a contact element applies a downward force to the vertically mountable semiconductor device to establish and maintain an electrical connection between the vertically mountable semiconductor device and the carrier substrate.

公开(公告)号：US20060030072A1

公开(公告)日：2006-02-09

申请号：US11219214

申请日：2005-09-01

Applicant: Larry Kinsman ,  Walter Moden ,  Warren Farnworth

Inventor： Larry Kinsman ,  Walter Moden ,  Warren Farnworth

IPC: H01L21/50

CPC classification number: H05K3/301 ,  H01L25/105 ,  H01L2225/107 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K2201/10454 ,  H05K2201/10696 ,  Y10S83/942 ,  Y10T29/49121 ,  Y10T29/4913 ,  Y10T29/49135 ,  Y10T29/49147 ,  Y10T29/49156 ,  Y10T29/49169 ,  Y10T29/53174 ,  Y10T29/53178 ,  H01L2924/00

Abstract: A method for securing a semiconductor device to a carrier substrate includes inserting a semiconductor device with a plurality of stub contacts extending from a bottom edge thereof into a receptacle of an alignment device associated with the carrier substrate. Upon attachment of the alignment device to a carrier substrate and insertion of a vertically mountable semiconductor device into the receptacle, the semiconductor device is biased so as to establish and maintain electrical communication between the semiconductor device and the carrier substrate.

公开(公告)号：US20060001155A1

公开(公告)日：2006-01-05

申请号：US11219135

申请日：2005-09-01

Applicant: Larry Kinsman ,  Walter Moden ,  Warren Farnworth

Inventor： Larry Kinsman ,  Walter Moden ,  Warren Farnworth

IPC: H01L23/04

CPC classification number: H05K3/301 ,  H01L25/105 ,  H01L2225/107 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K2201/10454 ,  H05K2201/10696 ,  Y10S83/942 ,  Y10T29/49121 ,  Y10T29/4913 ,  Y10T29/49135 ,  Y10T29/49147 ,  Y10T29/49156 ,  Y10T29/49169 ,  Y10T29/53174 ,  Y10T29/53178 ,  H01L2924/00

Abstract: A semiconductor device package including leads with substantially planar exposed portions extending from a bottom edge of the package. The exposed portions of the leads may comprise stub contacts extending perpendicularly from the bottom edge. The exposed portions of the leads may be substantially rigid or nondeformable. A complementary alignment device that may be used with the semiconductor device package may include a receptacle for receiving the semiconductor device package.

Abstract translation: 一种半导体器件封装，包括具有从封装的底部边缘延伸的基本平坦的暴露部分的引线。 引线的露出部分可以包括从底部边缘垂直延伸的短截线。 引线的暴露部分可以是基本上刚性的或不可变形的。 可以与半导体器件封装一起使用的互补对准装置可以包括用于接收半导体器件封装的插座。

公开(公告)号：US06914198B2

公开(公告)日：2005-07-05

申请号：US10237579

申请日：2002-09-09

Applicant: Salman Akram ,  Warren M. Farnworth ,  Alan G. Wood ,  J. Michael Brooks ,  Eugene H. Cloud

Inventor： Salman Akram ,  Warren M. Farnworth ,  Alan G. Wood ,  J. Michael Brooks ,  Eugene H. Cloud

IPC: H01L23/495 ,  H05K1/02 ,  H05K1/09 ,  H05K3/32 ,  H05K1/18

CPC classification number: H05K3/4007 ,  H01L23/4951 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181 ,  H05K1/0271 ,  H05K1/095 ,  H05K3/321 ,  H05K3/325 ,  H05K3/326 ,  H05K2201/0133 ,  H05K2201/0314 ,  H05K2201/0367 ,  H05K2201/09909 ,  H05K2201/10454 ,  H05K2201/10696 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Disclosed is a device comprising a circuit having an active side and a non-active side, a package enclosing the active side of the circuit and not enclosing a portion of the non-active side of the circuit, and a lead having a first end connected to the active side of the circuit via a lead-over-chip connection, and having a second end extending from the package. Also disclosed is a device comprising a circuit and a lead formed from a flexible conductor, with the lead having a first end connected to the circuit.

Abstract translation: 公开了一种包括具有有源侧和非有源侧的电路的器件，封装电路的有源侧的封装，并且不包围电路的非有源侧的一部分，以及引线，其具有连接到第一端 经由引线芯片连接到电路的有源侧，并且具有从封装延伸的第二端。 还公开了一种包括由柔性导体形成的电路和引线的器件，其中引线具有连接到电路的第一端。

公开(公告)号：US06858453B1

公开(公告)日：2005-02-22

申请号：US09416368

申请日：1999-10-12

Applicant: David J. Corisis ,  Tracy Reynolds ,  Michael Slaughter ,  Daniel Cram ,  Leland R. Nevill

Inventor： David J. Corisis ,  Tracy Reynolds ,  Michael Slaughter ,  Daniel Cram ,  Leland R. Nevill

IPC: G01R1/04 ,  G01R31/28 ,  H01L23/495 ,  H01L23/544 ,  H05K3/30 ,  G01R31/26 ,  H01L21/00 ,  H01L21/44 ,  H01L21/48 ,  H01L21/66

CPC classification number: G01R31/2851 ,  G01R1/0408 ,  G01R31/2884 ,  H01L23/4951 ,  H01L23/544 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/54473 ,  H01L2223/54486 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/49171 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/181 ,  H05K3/303 ,  H05K2201/10568 ,  H05K2201/10689 ,  H05K2201/10696 ,  H05K2203/167 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2924/00012

Abstract: An integrated circuit is provided having an alignment feature integral with the lead frame. The integrated circuit includes a lead frame coupled with a semiconductor die, and is partially encapsulated in insulating material. The lead frame has the alignment feature therein. The alignment feature includes a cut out on the lead frame taking the form of a semicircle, protuberance, apertures, or slots. Alternatively, the alignment feature includes a removably coupled tab. After testing of the integrated circuit has been completed, the alignment tab is removed from the integrated circuit. The alignment feature can also be provided on a heat spreader which is attached to a side of or within the lead frame package.

Abstract translation: 提供了具有与引线框一体的对准特征的集成电路。 集成电路包括与半导体管芯耦合的引线框架，并部分封装在绝缘材料中。 引线框架具有其中的对准特征。 对准特征包括在引线框架上切割出半圆形，突起，孔或槽的形式。 或者，对准特征包括可移除地耦合的突片。 集成电路测试完成后，对准标签从集成电路中取出。 对准特征也可以设置在附着于引线框架封装的一侧或内部的散热器上。

公开(公告)号：US20030198020A1

公开(公告)日：2003-10-23

申请号：US10457122

申请日：2003-06-09

Inventor： Larry D. Kinsman ,  Jerry M. Brooks ,  Walter L. Moden

IPC: H05K007/20

CPC classification number: H05K3/303 ,  H01L23/3675 ,  H01L23/4334 ,  H01L2924/0002 ,  H05K1/0203 ,  H05K2201/09709 ,  H05K2201/10454 ,  H05K2201/10659 ,  H05K2201/10696 ,  Y02P70/613 ,  H01L2924/00

Abstract: A high density vertical surface mount package and thermal carrier therefore including a heat sink.

Abstract translation: 因此，高密度垂直表面安装封装和热载体包括散热器。

公开(公告)号：US20030111718A1

公开(公告)日：2003-06-19

申请号：US10352698

申请日：2003-01-27

Inventor： Larry D. Kinsman ,  Walter L. Moden ,  Warren M. Farnworth

IPC: H01L023/02

CPC classification number: H05K3/301 ,  H01L25/105 ,  H01L2225/107 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K2201/10454 ,  H05K2201/10696 ,  Y10S83/942 ,  Y10T29/49121 ,  Y10T29/4913 ,  Y10T29/49135 ,  Y10T29/49147 ,  Y10T29/49156 ,  Y10T29/49169 ,  Y10T29/53174 ,  Y10T29/53178 ,  H01L2924/00

Abstract: A vertically mountable semiconductor device including a plurality of stub contacts extending perpendicularly from a bottom edge thereof. A complementary alignment device includes a receptacle for receiving the vertically mountable semiconductor device. The alignment device is attachable to a carrier substrate. Upon attachment of the alignment device to a carrier substrate and insertion of a vertically mountable semiconductor device into the receptacle, a contact element applies a downward force to the vertically mountable semiconductor device to establish and maintain an electrical connection between the vertically mountable semiconductor device and the carrier substrate.

Abstract translation: 一种可垂直安装的半导体器件，包括从其底部边缘垂直延伸的多个短截线触头。 互补对准装置包括用于接收垂直安装的半导体器件的插座。 对准装置可附接到载体基板。 在将对准装置附接到载体基板并将可垂直安装的半导体装置插入到插座中时，接触元件向垂直安装的半导体器件施加向下的力，以建立并保持可垂直安装的半导体器件与 载体衬底。