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公开(公告)号:DE10346312A1
公开(公告)日:2005-05-04
申请号:DE10346312
申请日:2003-10-06
Applicant: INFINEON TECHNOLOGIES AG
Inventor: WERNER WOLFGANG , THIHANYI JENOE
IPC: H01L21/761 , H01L29/41 , H01L29/78 , H01L21/76 , H01L27/06
Abstract: The semiconductor component (1'), with several semiconductor function elements connected in series or parallel, has 2 superimposed semiconductor layers (2,3) with opposite dopings, an insulation structure (4,5) formed in the upper semiconductor layer, for dividing it into relatively isolated semiconductor regions (6,7,8) for respective function elements, e.g. metal oxide silicon field effect transistors. The insulation structure is at least partially formed of a metal/silicide (15).
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公开(公告)号:DE10324377A1
公开(公告)日:2005-01-05
申请号:DE10324377
申请日:2003-05-28
Applicant: INFINEON TECHNOLOGIES AG
Inventor: WERNER WOLFGANG , OTREMBA RALF , ROEDIG HERBERT
IPC: F28F13/00 , H01L23/367 , H01L23/373 , H01L23/36 , B82B1/00
Abstract: The heat extraction device, especially a thermal cable (10), is designed to transfer a quantity of heat from a heat source (WQ) to a heat sink (WS) and has a nanotube arrangement (20) with a number of nanotubes (30) as a material for heat extraction or a part of it. The nanotubes are embedded in an embedding material, especially an adhesive material. An independent claim is also included for the following: (a) a semiconducting component arrangement.
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公开(公告)号:DE10239310A1
公开(公告)日:2004-03-25
申请号:DE10239310
申请日:2002-08-27
Applicant: INFINEON TECHNOLOGIES AG
Inventor: FISCHER HERMANN , WERNER WOLFGANG , MAYER THORSTEN , KANERT WERNER , FUGGER JOSEF
IPC: H01L29/417 , H01L29/78 , H01L21/28 , H01L21/336
Abstract: Production of conducting connection between first trenched layer (2) of first conductivity arranged at distance from front side (101) of semiconductor body (100) and second layer (4) of second conductivity comprises forming recess from front side to first layer, and doping via recess into boundary region between first and second layer to produce strongly doped connecting zone (3). Production of an electrically conducting connection between a first trenched layer (2) of first conductivity arranged at a distance from a front side (101) of a semiconductor body (100) and a second layer (4) of a second conductivity comprises forming a recess (6) extending from the front side up to the first layer, and introducing doping atoms of first and second conductivity via the recess into a boundary region between the first layer and the second layer to produce a connecting zone (3) in the boundary region which is more strongly doped than the first layer forming a tunnel diode with the second layer.
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公开(公告)号:DE10006519B4
公开(公告)日:2004-03-11
申请号:DE10006519
申请日:2000-02-15
Applicant: INFINEON TECHNOLOGIES AG
Inventor: TIHANYI JENOE , WERNER WOLFGANG
IPC: H01L27/07 , H03K17/0814 , H03K17/687 , H03K17/695 , H01L27/088 , H01L21/8234 , H01L23/60 , H03K17/64
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65.
公开(公告)号:DE10100282A1
公开(公告)日:2002-07-18
申请号:DE10100282
申请日:2001-01-04
Applicant: INFINEON TECHNOLOGIES AG
Inventor: STRZALKOWSKI BERNHARD , WERNER WOLFGANG , STENGL JENS-PEER
Abstract: Transformer comprises a first coil (20) and a second coil (40) formed in displaced surfaces of a semiconductor device. An Independent claim is also included for a process for the production of a transformer comprising preparing a first semiconductor body (10) and forming the first coil on the surface of this body or in the body; preparing a second semiconductor body (30) and forming the second coil on the surface of this body or in the body; and applying the second semiconductor body on the first semiconductor body. Preferred Features: The coils are formed as spiral-like conducting pathways. The first coil is covered with a first insulating layer (14) in the region of the first semiconductor body and the second coil is covered with a second insulating layer (36) in the region of the second semiconductor body. The first coil is further covered with a third insulating layer (70).
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公开(公告)号:DE10062637A1
公开(公告)日:2002-07-04
申请号:DE10062637
申请日:2000-12-15
Applicant: INFINEON TECHNOLOGIES AG
Inventor: KOLB STEFAN , WERNER WOLFGANG
Abstract: Micro-machined differential pressure sensor comprises a substrate (1) with a hollow space (3) on one side of a main surface (2). The space is delimited by a movable membrane (4), a doped silicon wall (6) and an isolating layer (5). An opening (12), which is connected to a medium at a second pressure, connects to a channel (13) linking it to the hollow space. The hollow space, movable membrane and doped wall form a capacitor that is used to measure differential pressure. An analysis circuit is formed on the main surface of the pressure sensor.
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公开(公告)号:DE19600400C2
公开(公告)日:2002-05-16
申请号:DE19600400
申请日:1996-01-08
Applicant: INFINEON TECHNOLOGIES AG
Inventor: WERNER WOLFGANG
IPC: H01L29/84 , B81B1/00 , B81C1/00 , G01P1/02 , G01P15/08 , H01L21/306 , H01L21/316 , B81B3/00 , H01L21/308 , H01L21/31 , H01L21/311
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公开(公告)号:DE19902749C2
公开(公告)日:2002-02-07
申请号:DE19902749
申请日:1999-01-25
Applicant: INFINEON TECHNOLOGIES AG
Inventor: WERNER WOLFGANG
IPC: H01L27/085 , H01L29/08 , H01L29/78 , H01L29/808
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公开(公告)号:DE10026925A1
公开(公告)日:2001-12-20
申请号:DE10026925
申请日:2000-05-30
Applicant: INFINEON TECHNOLOGIES AG
Inventor: WERNER WOLFGANG
IPC: H01L29/08 , H01L29/10 , H01L29/45 , H01L29/739 , H01L29/78
Abstract: The field effect semiconductor has a semiconductor body (1) provided with at least one inner zone (2) of one conductivity type, incorporating at least one base zone (4) of opposite conductivity type at the surface (3) of the semiconductor body, in turn incorporating a source zone (5) with the same conductivity as the inner zone. A further base zone (15) is separated from the first base zone by an intermediate zone (16) with the same conductivity as the inner zone. A source contact zone (17) provides a low-ohmic connection between the source zone, the base zone and the further base zone.
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公开(公告)号:DE10026742A1
公开(公告)日:2001-12-13
申请号:DE10026742
申请日:2000-05-30
Applicant: INFINEON TECHNOLOGIES AG
Inventor: WERNER WOLFGANG
Abstract: A FET (T1) has a gate terminal (G) coupled to control terminal (K1), and a source terminal (S) coupled to first load terminal (K2). To the second load terminal (K3) is linked the drain terminal (D), while there is also a substrate terminal (sub). A bipolar transistor (T2) comprises a base terminal (B), an emitter terminal (E), and a collector terminal (K) with the emitter terminal coupled to the FET substrate terminal. The base and collector terminals are also linked to the first load terminal.
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